networkZONE Products for the week of December 9, 2002
Agere Says . . .
A ray Of Hope - Agere's FlexPHY Versatile Single-Chip
PHY Bets On Recovering 10-Gbit Markets
PHY Delivers Low Power, Low Jitter, Low Cost solutions For
OC-192, 10G Ethernet, and 10Gbit FibreChannel
Agere Systems Inc. has unleashed its FlexPHY IC, a new single-chip physical layer (PHY) transceiver that reduces space and power by more than 50 percent over existing two-chip solutions, and enables the highest transmission signal quality for today's multi-service metropolitan edge to core networks. The FlexPHY device breaks all performance records of previous Agere PHY chips, offering the industry's best performance, jitter margins, power consumption and integration, while lowering costs and speeding time-to-market for system vendors targeting 10-gigabit SONET/SDH and Ethernet (10 GE) and Fibre Channel (10 GFC) networks. Samples of the FlexPHY chip are expected to be available in the first quarter of calendar year 2003, with volume production expected by the second quarter of 2003.
The market for 10-gigabit PHYs is one shining spot of growth in the capex-constrained telecom market. This product segment is expected to increase from $276 million in sales in 2003 to $780 million in 2006, according to Sean Lavey, an analyst with IDC.
Rich feature set enables higher performance, port density and functionality
A PHY transceiver chip transmits and receives data between the physical (optical fiber) and information processing layers. On a network line card, Agere's FlexPHY chip resides at the boundary between the protocol framer and the optics, providing the bridge for improved, multi-rate optical performance with multi-protocol support for the framer. Agere recently introduced its MARS (Multi-Application and Rate Solutions) family of chips, the industry's most integrated and versatile framers for multi-service metropolitan and access networks.
The FlexPHY chip has more than double the density of competitive offerings and uses industry-leading multi-rate, multi-protocol, signal integrity technology.
No other PHY in the market today comes close to matching the FlexPHY chip's tested and proven low power consumption, small size, high performance and multiplicity of features. As such, the FlexPHY IC can be used in more communication network applications than comparable chips, from ATM and Ethernet switches and routers connecting data centers and IT infrastructure, to multiplexers and dense wave division multiplexed (DWDM) optical backbone transport systems.
The FlexPHY chip's jitter generation is as low as 30 milli-unit interval (mUI) peak-to-peak (p-p) -- the industry's best performance in this critical metric. Most competitive single-chip CMOS devices have jitter generation of greater than 50 mUI p-p. A typical network system jitter generation budget is typically 100 mUI p-p. The low generated jitter allows for additional flexibility in system design and makes the FlexPHY chip suitable for all optical networking applications from very short reach (VSR) to ultra-long reach (ULR), including DWDM.
To reduce board real estate, increase performance, flexibility and functionality, the FlexPHY chip integrates a clock multiplier unit (CMU), 16:1 multiplexer and 1:16 demultiplexer functions into a single device. It incorporates a highly sensitive (less than 10 mV) limiting amplifier with programmable amplitude threshold adjustment, as well as clock data recovery (CDR) function with programmable phase sampling point adjustment. These features extend the reach of the FlexPHY chip to ULR applications that are not both available in competitive single-chip devices.
Enhancing performance and reliability, the FlexPHY IC offers the lowest power consumption on the market. It has a total average power consumption of 1.0 W versus most competitive solutions' 1.4 W to 2.0 W of power consumption. The FlexPHY chip's low power specification is key to developing high-density board designs for space-constrained equipment, improved performance and reliability.
Agere's FlexPHY chip is manufactured in 0.13 micron CMOS technology,
which
contributes to higher performance, integration, versatility and functionality
while at the same time lowering power, space and system development costs.
As a result, the FlexPHY chip supports a wide range of protocols, rates
and reach.
It addresses 10 GE 10.31 Gbits/s), 10 GFC (10.52 Gbits/s), OC-192 (9.95 Gbits/s), OC-192 forward error correction (FEC) (10.66 Gbits/s) and G.709 FEC (10.71 Gbits/s) rates. Further reducing space, power and cost, the FlexPHY IC integrates numerous previously discrete functions into a single system-on-chip (SoC), eliminating most external components.
"The FlexPHY chip further expands Agere's extensive family of reliable,
industry-leading multi-rate, multi-protocol solutions for network connectivity
and strongly leverages our integration and systems-level IC capabilities,"
said Kouroush Matloubi, marketing manager for PHY ICs with Agere Systems.
"With the industry's broadest portfolio of multi-application communication
IC solutions, we make it easier for customers to develop, build and deliver
complete, scalable to 10 Gbit/s systems to market. Our expertise with strategic
line card devices such as the FlexPHY devices allows us to deliver the lowest
cost per kilometer per port solutions in the industry." Agere's FlexPHY
chip is well suited for high-performance, direct line card implementation
as well as integration into optical transport modules. It is fully supported
by Agere's world-class applications, sales and marketing teams. Complete
data sheets, for the FlexPHY chip (refer to device number TSCV01010G) as
well as reference and evaluation platforms, are available. Agere expects
to price volume production FlexPHY devices at $250 each in quantities of
less than 1000 units.
analogZONE Says . . .
I fervently hope that Kouroush Matloubi, marketing manager of the FlexPHYs was not been partaking of too many hallucinogenic substances when he decided that OC-192 market should be recovering some time soon, and committed to producing this ambitious one-chip 10-Gbit/s PHY chip. Indeed, it would be a boon to many of us in the industry if Matloubi's belief that the glut of bandwidth we've suffered under for the past two years is about to be consumed in either the enterprise, metro, or long-haul markets is accurate, and the next year sees the beginning of a migration to OC-192 equipment. While optimistic, the folks at Agere are also practical and realize that they cannot predict exactly which markets will take off first, and have developed a clever chip that covers nearly all of them.
To accomplish this multi-role mission, the FlexPHY 10-Gbit/s PHY has a wide enough operating bandwidth to run at the data rates of SONET/SDH, 10G FibreChannel, and 10G Ethernet - Operating at 9.95 Gbit/s to 10.71 Gbit/s data rates. To boot, its OC-192 mode comes with integral FEC.
The front-end sections of Agere's current product 10-Gbit/s product lines are manufactured in SiGe, but the introduction of the FlexPHY marks the beginning of a migration to 0.13 micron CMOS. While this makes me a tad nervous, the higher density supported by the process allows the level of integration required to move from a two-chip to a one-chip solution. Since I've seen at least one other company come close to matching full SiGe performance, I'll take Agere's word that they can do this for the small handful of PLLs and other critical elements that operate at the full clock speed. Besides cutting the cost for this chip, the migration to CMOS also allows the PHY to become a handy piece of IP for more highly-integrated products.
Hooking up the FlexPHY is no problem, thanks to its straightforward SFI-4.0 interface (16-bit parallel) interface. Depending on your application's requirements, it can work with or without an external FEC chip. Should it be needed the PHY supports rates to 10.71 Gbit/s to handle overhead generated by FEC. And should you need to run an external laser or modulator PMD, the PHY can be connected directly to nearly any standard PMD device.
Despite the fact that it is built in CMOS, Agere claims it has near-SiGe jitter performance thanks to a novel CDR architecture that uses three PLLs. - one each for TX and RX, plus a jitter attenuator for the reference clock. This extra PLL can be used to stabilize and clean up external clock, providing jitter generation as low as 30mUIpk-pk in a 100 ps window. The CDR has an adjustable phase sampling point and the receiver has an adjustable threshold - no single-chip devices have both features, they usually have threshold adjustment but not phase though dual-chip devices do have both. The sample phase point is digitally controlled through a register while the threshold is an analog setting.
The device also packs an internal limiting amplifier that Agere says matches the performance of an external GaAs device. They told me that its customers were quite skeptical at first and did not expect that its sensitivity would be the same, but lab tests indicate that the part performs as well as a much more expensive multi-chip solution.
Given the fact that Agere wants to cover as much of the market as possible with a single chip, it's not surprising that much like the recent SerDes from Quake, it can go directly into MSA transponders or directly onto line cards for lower costs.
Of course Agere is not stopping to wait for the competition. They are continuing with their assumption that the OC-192 market is on the verge of recovery and have a lower-cost short-haul version in the works for later in '03. More than ever, I certainly hope their optimistic prognostication proves to be correct.
Sampling to Alpha partners now, availability sampling
expected 1Q 2003, with volume in 2Q 2003.
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