networkZONE Products for the week of November 3, 2003
Bay Microsystems Says…
Classy Classifier -- Bay Microsystems' Low Power,
Low Cost Programmable Classification Processor Can Parse, Classify and Police
Packets and Cells At OC-192/OC-48, and Beyond
Bay Microsystems, a leader in high performance packet processing,
announced Biscayne, a programmable classification processor that can parse,
classify and police packets and cells at rates up to 16 Gbits/s, at minimum
packet size regardless of traffic patterns. At 16Gbits/s for both ingress
and egress, and with power dissipation of only four watts, Biscayne is the
industry's lowest power classification processor.
Biscayne connects seamlessly to Bay's other Internetworking Processor (InP) products, including Montego, a single chip OC-192c/10G programmable internetworking processor, traffic manager and SAR. Based on the same deterministic, superscalar, pipelined architecture as Montego, Biscayne's classification and policing functions support a wide range of existing and emerging applications, including Ethernet, IPv6, IPv4, ATM, Packet over SONET, Frame Relay, MPLS and DiffServ.
Biscayne's unique features include dedicated policing algorithms, such
as Committed-Max-Excessive, Dual Token Bucket, and Dual Leaky Bucket, thus
supporting Ethernet/Frame Relay, DiffServ and ATM policing. This industry-first
policing support allows for policing on a flow or tunnel/trunk basis. Additionally,
Biscayne supports Quality of Service (QoS) internetworking, which allows
for programmable conversion from any QoS mark to any other QoS mark. Therefore,
QoS marks may be translated between protocols by user-defined rules and
relative QoS values may be retained
across disparate networks.
With this breadth of service support, Biscayne preserves investments in legacy equipment and enables new profitable services within the same equipment. While other classification processors only support parsing and classification tagging, Biscayne also enables modification functionality as well, making it an attractive option for cost-sensitive applications such as access enterprise equipment.
According to recent market research, Ethernet is becoming ubiquitous
across most metro and transport platforms, with metro Ethernet switching
projected to top $3 billion by 2006, (Infonetics Research (San Jose, CA)).
Biscayne enables this market with support for features such as fast path
MAC learning and aging, L2VPN, L3VPN, VPLS, VLANs with multiple domains,
and more. Additionally, with the proliferation of wireless devices driving
the need for more addresses and the US Government requiring IPv6 support,
IPv6 is gaining traction. Biscayne addresses the needs of IPv6 enabled switches
and
routers, including header popping for tunnel termination.
"Bay Microsystems was the first to deliver a single chip 10G network processor, traffic manager, and SAR, and it has now unveiled the industry's fastest classification processor," said Bob Wheeler, senior analyst at The Linley Group. "The combination of Biscayne and Montego should be attractive for deeply encapsulated metro applications. Bay's solution also offers excellent time-to-market through greatly simplified software development."
"Biscayne is another example of the superior Bay technology, which not only satisfies the current market requirements of our existing clients, but grows a family of products that spans a multitude of enterprise and carrier applications from access to long-haul," said Chuck Gershman, president and CEO of Bay Microsystems. "As we emerge from this long harsh market downturn, only the companies that can enable a wide range of market segments will thrive."
For high performance applications, Biscayne enhances the classification
capabilities of a downstream network processor/traffic manager, while providing
direct physical and messaging-based interface between the two devices. With
Biscayne, network systems OEMs can accomplish more complex tunnel resolution
and routing for products such as multi-protocol edge routers and voice/wireless
gateways. Biscayne is capable of classifying extra long headers, such as
IPv6; larger stacks of label swapping protocols,
such as MLPS; and highly complex and deeply embedded multi-field headers,
such as VLAN/SNAP, IPv6/IPv4. In addition, OEMs can now support applications
for Ethernet bridges/switches, VLAN forwarding, IETF PPVPN (VPLS, L2/L3VPN),
MPLS, VLAN to MPLS mapping, IETF PWE3 (ATM and Ethernet PR tunneling), Legacy
UNI (Frame Relay and ATM), and more.
Biscayne supports flexible packet parsing and key generation with direct interfaces to TCAM and SRAM search memories to support more than 400 million searches per second. Use of external memories allows the user to scale the memory to the application, enabling system cost to map directly to performance requirements. Biscayne interfaces to any SPI-4.1, SPI-4.2 or SPI-3 compliant device, thus supporting OC-48 and OC-192 applications.
Bay's robust simulation and emulation design environment, called the
Internetworking Development System (IDS), fully supports Biscayne. It includes
Java GUIs, CLI, Nextware API, System Administration Server (SAS), Intermodule
Communication, Vxworks OS, Board Support Package (BSP), Diagnostics, TCP/IP
Stack and Drivers. The Nextware software programming environment uses a
cycle/pipeline accurate C-simulator for quickly applying, verifying and
debugging application examples for any traffic pattern and network service.
analogZONE Says . . .
Wow, the folks at Bay Micro have been busy since I reviewed the Montego, their pipelined 10-Gbit/s network processor, back in April of 2002. While their claims at the time seemed rather difficult to believe at first, their working alpha silicon earned them one of the lowest "saltshaker ratings" I have handed out for a part with this complexity. And somebody else must have taken them seriously because they have been running in operational carrier-class equipment, supporting 10 Gbit/s of real, live traffic since April of this year.
But even all the processing power that the Biscayne delivers may not meet the demands of today's systems that will support extensive per-flow QoS and policy enforcement, and the peculiar requirements of emerging metro Ethernet networks. Bay is betting on the rapid expansion of Ethernet into the metro and access market -- a trend that's booming in the Far East and is expected to catch on here as North America's economy improves. Besides cleverly re-purposing Bay's pipeline architecture to do raging-fast recursive look-ups, their new auxiliary processor offloads the tasks involved with service internetworking and maintenance of services and features across network boundaries, and even across protocols (IP to ATM or FR, and back).
"You're beginning to see Ethernet and QoS in the same sentence" says Chuck Gershman, CEO of Bay, "but it's easier said than done." He explained that you can't simply shovel Ethernet from a LAN to a WAN environment without adding mechanisms to add reliability and QoS provided by ATM and FR. Gershman continued "Ethernet's protocols are not inherently friendly to the service capabilities ATM access systems have at the moment, such as QoS with full per-user prioritization, SLA enforcement with policing capability, VC/VPN support."
The Biscayne chip helps implement these critical service features to IP-v4/6 traffic by doing what Bay calls "stateful, recursive searching" which goes way beyond simple forwarding.. To put this in a de-jargonized way, their processor can do long searches anywhere within the packet headers and payloads, and then use the results to be passed to the next search as a parameter, pointer, or rule. This allows the results of a previous operation to modify the next search and perform layer-3/4decisions that are much longer, deeper, and harder to find than standard layer-2 lookups.
The algorithmic search capability lets a router tease apart multiple encapsulations of packets and policing for FR, ATM, DifServ, MPLS at wire speed. And, for the first time, you can also do policing of Ethernet traffic at the MAC level or on trunked collections of IP streams. Of course you could do this with a normal RISC-based network processor (is "normal NP" an oxymoron??), but it would really soak up the MIPs and drag down system performance to a crawl.
Biscayne also simplifies another difficult problem -- tagging for priority across system boundaries. The difficulty arises because different protocols use different fields for priority tagging, with different values and different meanings attached to them. Passing priority information across network boundaries requires that the priority field from each stream must be extracted from its original location and mapped to a value in the common terms used by the system. "QoS interworking" occurs when the data is shipped to another network, and the original priority field is re-mapped to a location and value understood by the other system The Biscayne gives you up to 4096 rules to base a decision on, for any of 256 enterprise IDs per port.
The other big issue in bridging IP onto a WAN environment is that it carries its control information within the packet that must support all functions (MAC learning, spanning tree, aging). They are normally supported by a control plane processor in an enterprise environment. This task gets infinitely more complex in a WAN where the number of users is orders of magnitude if the MAC tables for multiple enterprises are stored and maintained in a piece of metro Ethernet access equipment. MAC accountability has moved in towards the core. Biscayne offloads as much of this as possible at the edge to minimize control plane load so the router can concentrate on the rest of TCP stack and other tasks. Its TCAM-based table management eliminates most of the calculations required for updating table entries.
The choice to use off-chip memories helps keep down power and cost. Much like EZchip, Bay had to develop a scheme that works around the slower speeds available across an off-chip interface, a task they seem to have accomplished rather handily. Using commercial SRAM and TCAM chips also allows you a low-cost entry point (using smaller memory chips) which can easily be expanded as needed. Bay is currently working with Cybercore and IDT to supply reference designs using their TCAMs.
I asked Mr. Gershman about some of the very compelling claims made by some NP manufacturers who employ specialized logic that lets them use lower-cost SRAMs to implement classifiers. He says that SRAM-based search engines can handle forwarding problems, but fall down when confronted with more complex traffic management tasks the Montego and Biscayne are doing. Rather than trying to replace the TCAM which is becoming highly optimized and less costly, Bay is leveraging the power of other companies' TCAMs and all the features they offer. Bay also makes use of SRAMs (on multiple look-aside busses) for label identification and other direct map lookup tables that would underutilize the more expensive TCAM memory space. Depending on your application, you can map tables into SRAM or TCAM for optimum results.
In keeping with the Montego architecture, the Biscayne processor sports a robust set of interfaces that allows a straightforward hook-up to almost anything in your arsenal. The line-side allows you to connect via an SPI-3/4/4.2 interface, a10GE MII, or multiple 1-Gig Ethernet MACs. The system side uses the same physical connection options to facilitate easy hookup to any NP -- including the previously-reviewed Montego.
And speaking of the Montego chip, both of Bay's offerings now work directly with AMCC's (former IBM) Power PRS switch fabric (SPI 4.1 with CSIX overlay interface). It runs alone, or in series with Biscayne at 16 Gbit/s to accommodate the tagging overhead and overspeed requirements needed to keep the fabric transparent and non-blocking with large packets -- not bad for parts rated at 10-Gbit/s.
Despite the chip's complexity and the ambitious claims being made for it, the performance of its predecessor validates the architecture and Bay's ability to deliver. While I always worry about how a smaller silicon vendor will achieve market traction, it looks like Bay's unique combination of price and performance may win the day. And the unique capabilities the Biscayne brings to the party will only add to the momentum.
Biscayne will be sampling in Q1 2004 in a BGA-1156, in 166 MHz and 100 MHz versions priced below $300 in volume.
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