networkZONE Products for the week of November 1, 2004
Xelerated Says…
Xelerated Fine-Tunes Its Network Processor Architecture
For Ethernet Apps With 20 Gbit/s Full-Duplex, Plus 24 FE/GE MACs
Xelerated has doubled the throughput of its Xelerator X11 from
10G full-duplex to 20G full-duplex and embedded 24 FE/GE MACs. These changes
drop the cost per port by a factor of two, enabling the X11 to bring the
benefits of programmability to even more cost sensitive Ethernet applications.
Building on the industry leading X10q-e, the X11 utilizes an Ethernet optimized version of Xelerated's patented dataflow pipeline. This pipeline is significantly more compact than the Sonet optimized pipeline of the X10q, which has allowed 24 FE/GE MACs to be added, reducing the solution cost by a factor of two. The pipeline can be configured to support either 20G full-duplex Ethernet or 10G full-duplex Sonet applications. With built-in algorithmic search engines and direct attachment of DRAM, SRAM and TCAM, the X11 can support the optimum memory configuration for a wide range of applications.
"Due to its extremely high level of integration and flexible memory interfaces, the X11 can meet and in some cases beat the solutions cost for high-function Ethernet ASICs - all while providing the benefits of programmability," said Bob Wheeler, Senior Analyst at The Linley Group."This differentiates it from all other NPUs."
The X11 will supersede the X10q-e for 5G, 10G and 20G Ethernet applications as well as 5G and 10G Sonet applications, while the X10q-m and X10q-w will continue to be used for 20G Sonet applications. The X11 features SERDES interfaces for direct attachment to FE/GE/10GE PHYs or to XAUI-based switch fabrics, and dual SPI-4.2 interfaces for connecting Sonet framers or traffic managers. Each SPI4.2 interface supports up to 256 channels.
"Our customers demand flexible, future-proof Ethernet solutions
that are cost effective enough to allow them to compete against ASIC-based
solutions for 24xGE enterprise applications and mixed FE/GE metro Ethernet
applications," said Gary Lidington VP of Marketing at Xelerated. "To
meet these requirements, we optimized the X11 for Ethernet cost/performance
by doubling the number of Ethernet ports."
analogZONE Says . . .
With the introduction of this latest chip, Xelerated may have finally found the sweet spot for its novel and powerful architecture. Despite any quibbles with how they rated their capacity (which they have subsequently changed) I've always had a soft place in my heart for their unique configurable data flow processor. As I've detailed in previous reviews in July 2002 and May 2003, they offered deterministic, high-touch processing for both SONET/SDH and Ethernet/IP traffic with much more "crunch" per square millimeter of silicon (and per W) than other chips using conventional RISC engines at their heart. Their latest spin of the architecture has been optimized for Gigabit Ethernet applications where both the volume and competition is high. And in doing so, they seem to have found a point where they can deliver enormous performance and flexibility, at a price-per-port that challenges fixed-function silicon.
Without going into detail here (you can get that in my earlier reviews) the original X10 processor's 200-stage, 44-byte-wide pipeline was designed to provide equal support for SONET/SDH and Ethernet. This is great for internetworking and edge applications (about the only other processors with real Internet-working-oriented architectures are Wintegra's WinPath and Agere's PayoadPlus products), but the general-purpose architecture had its drawbacks. Perhaps the most significant issue was that the pipeline required 2 clock cycles to "swallow" a 64-byte minimum-size Ethernet packet --something which cut the chip's effective throughput in half for UDP and other short-packet traffic. Their first X11 processor (introduced late last year) widened the internal pipeline to 64 bytes. While the actual increase will vary by application, the wider data path adds around 50% more bandwidth by reducing the number of packets that have to be segmented plus, larger packets enjoy fewer segments.
The X11 also features a shortened pipeline (120 vs 200 stages). While this might seem like a downgrade at first, 120 operations are probably adequate for most L2/L3 applications and gives you lower latency. If you have a more complex function you need to implement, the X11 has an internal loopback mode that allows a packet to be tagged to let it run through multiple passes of the pipeline. The earlier X10 series could also loop selected packets, but it required an external connection and some engineering.
Xelerated put all the silicon real estate they
saved on the X11 to good use by adding on-chip search engines. The chip
has four 250-MHz DDR DRAM interfaces which allow you to implement multiple
tables without costly TCAMs. Now don't get me wrong, I'm a big TCAM fan
-- where it's appropriate. I have not seen anything that replaces them for
complex, irregular searches, but RAM-based search engines are perfectly
good for many simpler tasks such routing tables. In fact, the chip has its
own small internal TCAM (2 k), that can be used to accelerate many smaller
lookups. And if your application requires it, there's an external TCAM interface
that allows you to perform wide (up to 320 bits) lookups such as ACLs, filtering
rules, or extremely granular flow control which are often smaller data bases.
This combination of on-chip resources and off-chip interfaces lets you tightly
control BOM costs by tailoring any external memory you use to your application.
But Xelerated was not done. Before the original X11 hit the streets, they began work on expanding the family with a variant that was further optimized towards Ethernet by adding a pair of 10 Gbit/s interfaces (selectable 2 SPI 4.2/XAUI), and 24 on-chip Gigabit MACs that can also run as 2xXAUI. Since the new processor has 4 x 10 G interfaces it is now a 20 Gbit/s full-duplex part.
Its internal loop-back feature lets you send packets through up to five passes (if packet rate permits) to get up to 600 stages of processing. The processor's support for asymmetric looping lets it devote more time to either incoming or outgoing packets, something that makes balancing of ingress and egress processing easy. For example, its ingress processing capability allows it to buffer, filter, police and perform prioritized packet drops before they hit the switch fabric.
Although the X11 is optimized for Ethernet, you can still team the processor with an Infineon framer to add SONET capability without too much of a performance penalty. Infineon framer supports "full packet mode" which enables up to 256 channels over SPI interface without interleaving. This close linkage causes much less work for the processor which would have to otherwise spend some of its pipeline stages packets. If you want to run a different framer, the X11's 10GE ports can also run as channelized SPI-4.2 interfaces to support multiple streams but fragmentation adds to overhead.
Because
of the high level of functionality it delivers, the Xelerator X11's $395
price starts to look like a bargain for many applications. For one thing,
its doubled port count and effective processing capacity allows its cost
be spread over 24 (or more) ports. And that's not even considering the fact
that you eliminate the $100 - $150 you'd have to pay for separate MAC chips,
or the fact that most applications won't require external TCAM. If you're
really looking to cut the cost-per-port, the Xelerator supports intelligent
2:1-over-subscription.
The result is that for only slightly more than the price-per-port of a low-cost fixed-function merchant desktop/workgroup chip set, Xelerated lets you build a very flexible switch or router that can easily accept upgrades or support custom functions for product differentiation. You can even enhance a merchant chip set like Broadcom's StrataSwitch by using it as an outboard processor for a lowest-cost solution that still supports IPv6, MPLS and VPLS capabilities.
Moving up the product food chain a bit, Xelerated recently teamed with Dune to provide the fabric for a very cost-effective reference design that scales between 10-G pizza boxes through Terabit-sized enterprise/metro equipment.
When
I pointed out that Xelerated is trying to penetrate an already over-crowded
market, they explained that they think their architecture offers enough
advantages over its competition to become a significant contender. It should
be able to go head-to-head with EZ Chip in many applications because even
the EZ 210L is only a 10G full-duplex solution and provides only 10 Gigabit
Ethernet MACs (vs Xelerated's 24) at a similar price. The new X11 also gives
the Greenfield chip set's excellent cost/performance a run for its money
while delivering more flexibility, and has lower TCAM costs in most applications.
Despite these advantages, the big challenge Xelerated faces here is that they are a smallish vendor, with part of a solution and an unusual architecture that will take designers some time to get their heads around. The new X11 has enough compelling features and a high enough cost/performance ratio that it should help get it at least a first look. The reference designs from Broadcom and Dune, along with a good suite of straightforward development tools should bring many of them back for a second, closer look.
The Xelerator X11 is scheduled to sample Q1 2005
and will be priced at $395 for 10-k piece lots.
|
| ||||
