networkZONE Products for the week of October 28, 2002
EZchip Says . . .
C Is For "Can-Do" - EZchip's NP-1c, Next-Gen
10-Gbit Network Processor Adds Channelization, Doubles MIPS, Cuts Price
By 30%
EZchip Technologies, a fabless semiconductor company providing
high-speed network processors, today announced its second-generation 10-Gigabit
product - the NP-1c - further solidifying its leadership in the high-speed
network processors market. NP-1c is manufactured with IBM's leading CU-11
0.11 micron process and will feature a two fold processing power increase
and a 30% price reduction to $795 for a full-duplex 10-Gigabit network processor.
NP-1c is pin-compatible with NP-1 and is targeting a wide range of market segments including multi 1-Gigabit and 10-Gigabit Ethernet, OC-192, 4 x OC-48 and 16 x OC-12, all with a single-chip. NP-1c maintains NP-1's outstanding integration of Processing and Classification on a single chip, eliminating the need for power-hungry CAMs and SRAMs that costs hundreds and thousands of dollars, saving as much as 80% in chip-count, power dissipation and cost versus alternative solutions. NP-1c samples are scheduled for Q1 2003. EZchip will disclose information on the NP-1c at the Network Processors Conference West in San Jose, California on October 23, 2002.
"Since the introduction of NP-1 to the market we have witnessed an excellent reaction and design-win momentum from customers selecting EZchip for the huge cost reduction and extended product life-time that NP-1 is offering," said Eli Fruchter, president and CEO of EZchip. "While most of the competition is struggling with getting their first product out, we are broadening our product offering with NP-1c, our second-generation product, targeting the high-speed 10-Gigabit and OC-192 as well as multi 1-Gigabit, OC-48 and OC-12 with a single chip. Despite the current difficult market conditions, we are seeing continued growth in the number of customers that are selecting EZchip, a handful of which are large system vendors. Real paying customers that allocate engineering resources for designing EZchip based products, are a testament to customers' confidence in our long-term success and drive to become a leading player in this growing market."
"EZchip set the pace for the industry by delivering the first full-duplex 10GbE/OC-192 network processor earlier this year," said Linley Gwennap, principal analyst of The Linley Group. "While other vendors have yet to match the performance and integration of the original NP-1, the new NP-1c will deliver even more performance while reducing system cost and power."
The EZchip Advantage
Network processors are becoming the cornerstone of many new network equipment
designs because they significantly reduce the time to market and development
costs of new systems. EZchip's NP-1 and NP-1c bring additional value to
the equipment vendors by also reducing their production costs while extending
the time in market of their products. This is achieved through the unique
integration of Processing and Classifying, the two main functions of network
processing, onto a single NP-1 or NP-1c chip.
Unlike other network processors which require external devices for classification, namely CAMs and SRAMs, the NP-1 and NP-1c are based on EZchip's TOPcore® architecture, eliminating the need for any of these classification components. NP-1/NP-1c based solutions require only four low-power, low-cost DRAM chips for classification. Since the bit density of a DRAM chip is 30 times higher than that of a CAM chip, while its power dissipation and cost per bit are approximately 280 times and 1000 times lower respectively, NP-1/NP-1c dramatically reduce the total system chip-count, power and cost. Furthermore, network equipment based on NP-1 or NP-1c gain an extended time in market by the extensive headroom made available through the use of DRAM. New applications that often require more and larger lookup tables are supported through software updates only, without requiring the addition of any new hardware.
The advantages of NP-1 and NP-1c are clearly demonstrated in a wide range of applications, for instance support of IPv6, that vendors are implementing in the design of their next generation network products. The upsurge in IPv6 is linked to the growing shortage of available IP addresses, mainly in the Far East, and the upcoming deployment of 3G mobile networks with IP address assignment per individual wireless phone or hand-held device. The IPv6 address is four times longer than the current IPv4 address, 16 bytes versus 4 bytes, offering a virtually unlimited number of available IP addresses, however it also means that an IPv6 router's routing and session tables are approximately four times larger as well. While IPv6 processing requires no additional hardware in NP-1/NP-1c based routers, it significantly impacts the hardware required for designs based on other network processors.
For example, a 10-Gigabit interface of an IPv6 router requires a single NP-1c and four DRAM chips, same as for an IPv4 router, for a total cost of $820 and 17W power dissipation. With other network processors, the same interface would be implemented with two network processors and at least 20 (for small routers) and up to 80 additional CAM and SRAM chips producing a total cost of $3,000-$12,000 and 75W-300W power dissipation. At the same time, the EZchip-based solution provides an average of 80% headroom for growth versus alternative solutions with zero headroom. Therefore while support of new applications with NP-1/NP-1c is enabled through software updates, solutions based on other network processors would require a hardware redesign.
NP-1c Highlights
NP-1c offers the same outstanding advantages featured in NP-1 making it
the world's most integrated network processor. NP-1c reduces the total chip-count,
power dissipation and cost of packet processing and classifying by as much
as 80% versus alternative solutions.
NP-1c extends time-in-market of networking equipment by offering typically 80% headroom versus other network processors solutions often with zero headroom. System vendors using NP-1c do not need to add new hardware to support applications that require new classification tables, and can accommodate these simply through software upgrades.
Channelized SPI4.2 addresses the markets for OC-192 sub-rate applications, e.g. 4 x OC-48 and 16 x OC-12, in addition to the already addressed OC-192, multi 1-Gigabit and 10-Gigabit Ethernet applications.
Stateful classification addresses the need from equipment vendors for increasingly high throughput when provisioning advanced services such as server load balancing, virtual private networks (VPN) and content switching. With these applications the system CPU often becomes the throughput bottleneck. NP-1c alleviates this bottleneck by offloading many CPU control tasks to the NP-1c network processor.
NP-1 and NP-1c run the same software, employ the same package and use
the same pin-out for like interfaces to enable customers to easily port
of their designs from one device to the other.
analogZONE Says . . .
I guess I owe Eli Fruchter, EZchip's CEO, an apology. Although I was quite skeptical about his small band of battle-hardened siliconistias plans to deliver its highly ambitious NP-1 processor, a multi-stage, multi-CPU, programmable pipelined packet processor, the chip has been shipping since April. And despite the six-month delay in its arrival (which I did correctly predict), the NP-1 seems to be a pretty solid product that has garnered several significant sales, including a couple of name-brand players. The sales seem to have put the company into an enviable position, making it one of the few chip makers in the Valley to actually grow headcount (60 to 90 people) in the past year. So, based on Ezchip's past performance, I'll cut them some slack with the release of their NP-1c, an improved version of the NP-1shipping in Q1 2003.
The NP-1c uses the migration from the NP-1's 0.18 micron CMOS process to IBM's 0.11 micron (more like most company's 0.13 process) fab line to add performance and features, while dramatically slashing prices by 30%. This in effect throws down the gauntlet to competing NPs, and to the traditional ASICs that compete with NPs to meet a new price-performance benchmark.
EZchip's '1c shares much of the architecture and almost all of the instruction set of its predecessor. The guts of the machine still consist of four multi-processor stages that perform (in sequence) inspection and parsing based on header (and some content), searching for route addresses, address resolution, and packet modification. It also contains the gobs and gobs of on-chip memory, plus some very clever search tree logic that allows all buffering and lookup functions to be done using a couple of inexpensive DRAMs instead of the SRAMs and CAMs used by most other chip sets.
The new chip on the block adds channelization, an important feature for making efficient use of the existing SONET infrastructure that comprises the bulk of our metro access and long-haul networks. Using an external channelized framer from PMC-Sierra, the NP-1c can support 16 ports of OC-12 traffic, four ports of OC-48, and one OC-192 port. I think Fruchter and crew made a wise choice here since there will be lots of OC-48 and even OC-12 ports out there at the edge for quite some time to come. Another important upgrade to the NP-1 is its ability to provide time-shared interface to multiple low-speed ports via its SPI-4.2 interface, as well as the earlier XGMII / GMII / RGMII / TBI port interfaces. I applaud the choice to support SPI-4.2, since it is a very nice LVDS-based high-speed port technology that is on its way to becoming a standard for several different applications.
With the popularity of SPI-4.2, it's no wonder then that the NP1c also supports the SPI-4.2 version of the NPF's CSIX switch fabric interface. After a couple of years of struggling, the CSIX spec (under the wing of the NPF) is beginning to catch on and pay off on its promise. For one thing, the standard interface has allowed EZchip to partner with Broadcom, IBM, and ZettaComm, for switch fabric and PMC & Broadcom for PHY interfaces in reference designs.
The bottom line of their move to the 0.11 micron process is that they expect the shrink to double the processing power (through increased clock speed and more processors in each of the chip's functional blocks), plus a 30% cost reduction (we'll get to this in a minute.)
I'm reasonably confident in EZ Chip's claims that the '1C will provide sufficient processing punch and classification memory for many applications. Like the original NP-1, it uses a wide, fast internal DRAM (plus proprietary hash and tree algorithms) for classification and only results are stored externally with 1-2 accesses required per operation. This combination of speed and capacity lets the chip search through up to around 2 M table entries at OC-192wire speeds.
The above-mentioned DRAM interface can address up to 2 Gbyte of external memory, leaving considerable room for future requirements (a typical large route table requires 300 Mbytes today.) This is important for IPv6 apps which have huge route tables (four times IPv4), and a necessity in Far East where IPv6 is now the protocol of choice because of the huge numbers of ports coming on line every day.
With the NP-1 doing so well in the field, I only have a few concerns about some of the claims made for the NP-1c. It seems to me that the chip's fully-programmable architecture is at once its strength, and its potential point of vulnerability. The flexibility it affords lets it be used to provide specific services (VPNs, firewalls NAT) or other tasks at the blade, and can be reprogrammed as needed. On the other hand, I worry that even with the highly-optimized architectures used for each of the four blocks, they will not provide as much performance as fixed-function logic in really complex operations. I am also a little concerned about the fact that the four arrays of highly-specialized processors would prove a programming nightmare in situations where it became necessary to bypass EZchip's compiler and hand-code critical software elements. EZchip assures me that their current development software makes it possible to program each section as a single very conventional processor in a high level language - even for critical loops. They also say that the programmer's job have become even easier since they put their new development systems in people's hands 6 month ago. With customers' prototype systems already up and running in the labs they expect to see NP-1-powered products becoming available in early '03.
And of course, the other compelling issue is price.
Using some fairly reasonable assumptions, they claim up to an 80% reduction
in cost and parts count over other NPs and ASICs through elimination of
CAMS, SRAM , and other external components. Cost of a 10 G port can total
$1500 to $10K, vs. an EZchip NP-1c and four DRAMS for about $820 - significantly
less than many competing solutions.
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