networkZONE Products for the week of July 29, 2002
Motorola Says . . .
Quickest QUICC - Motorola PowerQUICC III Family Boasts
More Speed, More Intelligence And World's First Native RapidIO Interface
Leveraging Motorola's PowerQUICC III System-on-Chip Architecture,
the New MPC8560 Maintains the PowerQUICC Family Legacy of Performance and
Integration
The demand for faster, more sophisticated processing in the control
and forwarding planes of networking and telecommunications equipment is
driving a revolution in communications processors. Motorola revealed details
of its own technology revolution in its PowerQUICC III System-on-Chip (SoC)
Architecture-unveiling the company's first PowerQUICC III product implementation,
the MPC8560. Ideal for wired and wireless communications processing tasks,
the MPC8560 PowerQUICC III delivers the PowerQUICC family's renowned integration
together with performance headroom for intensive control plane processing
tasks and increased forwarding plane bandwidth.
Leveraging the comprehensive PowerQUICC III SoC Architecture, the MPC8560 employs a host of leading industry standards and innovative Motorola technologies-including a high-performance Book E PowerPC e500 core, an enhanced Communications Processor Module (CPM), RapidIO interconnect technology, Motorola's OCeaN crossbar switch fabric, dual Gigabit Ethernet interfaces, and support for Double Data Rate SDRAM (DDR SDRAM) and PCI-X.
"With the introduction of the PowerQUICC III family, Motorola closes its last remaining gap in the continuum of processors from CPE to the Optical Backbone," says Eric Mantion, Senior Analyst for In-Stat/MDR. "No other vendor can claim the breadth that is within Motorola's control and the Smart Networks Platform support structure that buoys the entire processor spectrum is truly world class. Motorola has continuously focused on making the arduous task of developing next-generation carrier equipment as painless as possible for its customers, and it shows."
The MPC8560 offers significant performance increases, with core speeds of up to 1 GHz and CPM speeds of up to 333 MHz. The CPM architecture retains software compatibility with the industry-leading PowerQUICC II family while offering greater than 1.0 Gbps aggregate bandwidth-in addition to the MPC8560's dual Gigabit Ethernet interfaces.
By using a SoC architecture in developing the PowerQUICC III family, Motorola is able to leverage a high degree of integration and future product flexibility. With the capability to add and customize specific processor elements, this SoC approach further enables the company to design and develop a variety of products targeted at specific application areas. Excitement is already building for Motorola's PowerQUICC III architecture from leading networking equipment manufacturers such as Alcatel.
"After a comprehensive study we have concluded that Motorola's PowerQUICC III architecture offered the combination of integration, performance and value we wanted for our next generation optical multi-service platform," stated Paolo Danielutti, vice president, Optical Multi-service Networks for Alcatel's optical networks activities.
"Motorola has been the market leader in this space since our introduction of the industry's first communications processor in 1989," said David Perkins, vice president and general manger of Motorola's Networking and Computing Systems Group. "Leveraging our PowerQUICC III architecture, the new MPC8560 adds to our strong portfolio of PowerQUICC and PowerQUICC II communications processors. Our innovative System-on-Chip methodology maintains our commitment to unsurpassed integration and provides our valued customers with a strong upgrade path and performance enhancements for years to come."
The MPC8560 - Highly Integrated for System Flexibility
The MPC8560 with its high degree of integrated functionality makes it an
ideal solution for integrated control and forwarding plane processing in
multi-service access platforms, central office switching and transmission,
wireless infrastructure, gigabit and terabit routers, voice gateway products,
IP Virtual Private Networks and optical networking equipment.
Unique features of the PowerQUICC III SoC Architecture and MPC8560 include:
Integration of the Book E PowerPC e500 Core
As with all PowerQUICC devices, the MPC8560 integrates control and forwarding plane tasks with a PowerPC ISA-based core and a Communications Processor Module. The MPC8560 offers a significant core performance increase, delivering operating speeds up to 1 GHz and providing greater headroom for control plane processing tasks.
The MPC8560 integrates a large 256KB on-chip memory array. Providing versatile options for customer design needs, the memory array is designed to support 8-way set associative L2 cache operation, memory mapped SRAM operation, or the array can be divided as a combination.
An Enhanced Communications Processor Module
The CPM performance has also been increased to 333 MHz, providing more internetworking bandwidth between ATM, TDM, Ethernet and other protocols while maintaining software compatibility with the PowerQUICC II CPM. The CPM contains two multi-channel controllers, four serial communications controllers, three fast communications controllers, eight time division multiplexed (TDM) interfaces, 32K bytes of dual port RAM, 128K bytes ROM plus 32 Kbytes of RAM for protocol microcode storage.
RapidIO Interface Support
Enabling high-speed connections to additional CPUs, peripherals or bus bridges, the MPC8560 employs the open standard RapidIO interconnect - the next generation high-speed interconnect for embedded applications. Supporting four priority levels with a maximum data payload of 256 bytes per packet, the RapidIO interface is engineered to deliver significantly greater bandwidth, scalability and reliability than interconnects used today.
Revolutionary OCeaN Crossbar Switch Fabric
Leveraging the concepts from Motorola's pioneering efforts in developing the RapidIO interconnect standard, Motorola's OCeaN (On-Chip Network) crossbar switch fabric provides cross-sectional bandwidth of up to 22 Gbps peak bandwidth per port, together with independent transaction queuing and flow control. This switch fabric implementation is designed to enable high bandwidth, high performance on-chip communication and to allow for the execution of multiple simultaneous data transactions.
Dual Gigabit Ethernet Interfaces
Including Layer 2 acceleration and Jumbo frame support, two full duplex Gigabit Ethernet interfaces are engineered to provide dataflow flexibility and easy connectivity for high-speed backplane or forwarding solutions.
Increased Memory and I/O Connectivity with DDR SDRAM Controller and PCI-X Support
With a DDR SDRAM controller designed to provide up to 333 MHz on a 64-bit dedicated bus with EEC support, customers can add up to 3.5 GBytes of system memory-increasing system performance, reliability and functionality.
Legacy support is enabled through an integrated 64-bit PCI-X controller, enabling easy connectivity to a variety of industry standard peripherals.
Common Software Tools Across the PowerQUICC III Family
Tools and software are planned to be supplied by Motorola and members
of Motorola's Smart Networks Alliance. Additional announcements regarding
third-party support are forthcoming.
analogZONE Says . . .
With even edge applications moving towards Gigabit speeds, Motorola's 8560 PowerQuicc III should be at least as much of a winner as its predecessor the PowerQUICC II series. The chip builds on the strengths of the QUICC family while addressing market trends which include the need for higher port density, higher data rates, more connectivity and aggregation capabilities, as well as internetworking capabilities (ATM, TDM, Ethernet to IP). The 8560 does this by offering higher performance levels, faster interfaces, and the addition of a switch fabric and the industry's first native RapidIO capability all indicate that Motorola has a very credible plan to continue its dominance in the communications processor market.
One of the more noticeable improvements is that the QUICCIII incorporates a much faster control processor. The "book E" PowerPC CPU is an architecture that was jointly defined by Mot and IBM which deleted several desktop extensions and added a few key features intended exclusively for increasing the performance of embedded applications. With clock speeds of between 600 MHz and 1 GHz, the e-series will deliver about double the performance of the QUICC II CPU.
The chip's communications processor (CPM) is faster (330 MHz), and has more ROM and memory space which can be used for more microcode, more user data protocol stacks and applications. Just like previous CPMs, you can "roll your own" microcode if needed to supplement the functionality after it is manufactured. And the nice thing is that all the code is compatible with QUICC II. And in addition to supporting, T/E1, T3/E3, plus 10/100 Ethernet, the comms processor now also supports Gigabit Ethernet.
One of the more exciting things about the 8650 its RapidIO (8-bit 500 MHz) controller. With RapidIO promising to be the interconnect of choice for most non-Intel processors, the first appearance of this fast, flexible, switched I/O bus on a processor is a welcome event indeed. Other speed enhancements include a move to 64-bit PCI bus.
There are lots of improvements in the memory department too, including a DDR RAM interface for extremely high-speed applications. Memory features also include a 32 K Li I-Cache, and D-Cache, (double the QUICC II's capacity) plus (New for the QUICC III ) a 256 K L-2 cache with 8-way set associative look-ahead. Interestingly, the L2 memory can be split to provide 16 K of fast on-chip system RAM if desired. Tools already under development from 3rd-party developers.
Motorola's architects have bit the bullet and added enough pins to let the LocalBus, RapidIO, and PCI be separate connections now, and not run through the same pins as in the QUICC II. This results in a whopping 784-pin device, but a tiny 1-mil pin pitch keeps the chip's footprint relatively small.
The result is a chip that combines control and data plane functions like previous QUICCs, but now supports data rates to OC-3 for Layer-2 applications. The CPM offloads its PowerPC host CPU from layer-2 protocol tasks so that it can run higher layer functions. This makes it a great candidate for internetworking applications of all kinds, and I expect to see 8650s and their variants populating lots of blades in access and edge applications where OC-3 and below are used extensively.
With tape-out anticipated for 4Q 2002, and samples in Q3 2003, I am reasonably sure Motorola should be able to deliver in this long-lead schedule. I worry a little that ambitious competitors may be able to use the long lead time to steal some of the potential sockets Motorola hopes to fill, but with the current slow market I think most applications can afford to spend the next year in development and be ready to go when the first chips arrive.
Pricing for a mid-range QUICC III will be around
$125 in early 2004 for 10-k quantities.
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