networkZONE Products for the week of July 17,
2006
Enigma Semiconductor Says…
Enigma Semiconductor's Linearly Scalable Packet Switching
Chipset
New Benchmarks Set for Density, Switching Efficiency and Flexibility
in Design of High Performance, Scalable Communications Platforms
Enigma Semiconductor has announced it is sampling the world's first linearly
scalable packet switching chipset. The chipset family, which features both
packet switches and a range of fabric managers, sets new benchmarks for
density, efficiency and flexibility. Based on Enigma's HybriCore architecture,
the chipset streamlines time-to-market for OEMs designing next-generation
metro access switches and routers, multi-service provisioning platforms
(MSPPs), enterprise routers and storage platforms.
Traditional shared-memory architectures offer limited system scalability,
while existing cell-based architectures are inherently inefficient. The
HybriCore memory-less crossbar switches announced today uniquely address
both of these challenges, scaling to support multiple-terabit configurations
and switching complete packets across the backplane to eliminate segmentation
and reassembly. This scalability and efficiency allows system architects
to future-proof their network and communications systems by ensuring that
next-generation line cards can be deployed within existing hardware infrastructure
platforms.
"With rising demands from both enterprise and carrier network providers,
the only way to achieve the next level of switching scalability is to break
the mold," said Rob Sturgill, president and CEO of Enigma Semiconductor.
"Finally, with the release of the HybriCore chipset, system architects
have a fully scalable packet-based switching system for building elegant
and robust carrier and enterprise equipment to support triple play applications.
These silicon building blocks support user-defined quality of service levels,
ultimately ensuring a positive user experience with these value-added, revenue-generating
services."
Density
A single HybriCore-based switch device switches up to 360 Gigabits per second
(Gbit/s) of non-blocking, full duplex traffic. Multiple switch devices scale
the design linearly to support multiple terabit system configurations that
have not been possible with legacy switching silicon. The fabric managers,
residing on the line card in a typical system topology, support 10, 20,
or 40 Gbit/s line card configurations and can be combined to achieve higher
density 80, 120 and 160 Gbit/s implementations. This device requires no
external buffer memory, which drastically reduces PCB footprint, system
power and system cost.
Efficiency
Legacy switch architectures typically convert packets into equal-length
cells, forcing a significant amount of backplane bandwidth to be used for
cell headers -- and in some cases, for partially empty cells. Maintaining
scalability with this legacy approach requires a substantial increase in
aggregate bandwidth across the backplane, increasing design complexity,
power and cost.
The HybriCore chipset achieves performance and scalability by switching
complete packets across the backplane, without the inefficiencies introduced
by segmentation and reassembly schemes typical of legacy switching architectures.
An intelligent scheduler ensures packets are transferred back-to-back across
the serial links, resulting in bandwidth utilization of greater than 98
percent. The scheduler also ensures high priority packets are switched with
very low latency, even when the switch is concurrently transporting large
packets.
Flexibility
Enigma has incorporated enhanced ABP (Advanced Backplane) technology from
Rambus, Inc., into the HybriCore chips to provide highly robust serial links
that support data rates from 2.5 Gbits/s through 12.5 Gbits/s. These serial
links integrate sophisticated equalization schemes to ensure reliable operation
despite changes in temperature, voltage and humidity. The family of HybriCore
chips supports a range of performance and price targets, providing design
flexibility for system architects.
Designed to Meet Stringent Network Requirements
Enigma delivers carrier-class network reliability with HybriCore's intelligent
backplane links that integrate multiple feedback loops and control paths.
The chipset is designed so that systems can use one of many available redundancy
schemes to deliver reliable failover mechanisms and maintain the highest
performance and reliability standards. This ensures the system will operate
reliably over long periods of time, regardless of environmental changes.
Product Descriptions
Enigma's HybriCore chipset family initially includes two packet switches
and three fabric managers. These devices can be mixed and matched to allow
system architects to make tradeoffs based on system power, performance and
cost requirements. The EN6105 integrated switch is optimized for use in
small modular chassis or "pizza box" applications that demand
minimal footprint, low power and low cost. The EN6110 is designed to address
massively scalable network equipment architectures, with the capability
to directly address up to 36 line cards.
The EN6210 Fabric Manager is a 10 Gbit/s single chip line card solution,
the EN6220 Fabric Manager is a 20 Gbit/s single chip line card solution
and the EN6240 is a 40 Gbit/s single chip line card solution. No external
buffer memory is required in designs based on these fabric managers, which
minimizes power dissipation and PCB footprint. The EN6200-family of fabric
managers incorporates industry-standard interfaces for direct connectivity
to a range of network processor units (NPUs), ASICs, and specialty packet
processing devices.
analogZONE Says . . .
Rather than jump into the already-crowded network
processor/traffic manager market, Enigma rolled out a series of switch fabrics
and fabric managers (line card interfaces) that can play with nearly any
packet processing device on the market. By providing a nicely scalable generic
switch fabric and a robust SerDes interconnect technology, Engma hopes to
sell its fabric into high-volume single-box SMB equipment as well as and
higher-end chassis-based (ie outside the pizza box) enterprise and carrier
products which have been dominated by Dune, Sandburst and ASICs.
The chip set consists
of a Fabric Manager and a Switch Fabric that are linked by a series of high-speed
(6.25 - 12 Gbit/s) SerDes channels. It is a pure switch device and relies
on external traffic managers and NPUs to perform classification, queuing
scheduling, and packet processing tasks (see Fig. 1). As we'll see shortly,
the Fabric Manager's generic SPI 4.2 interface makes it easy to use with
most third-party silicon, allowing designers to mix-and-match a system to
their needs rather than relying on a canned solution. Its open architecture
has also allowed this relatively small chip maker to enjoy an unusually
large ready-made ecosystem of first-line networking silicon to play with.
In fact, several of my favorite packet processing silicon makers are already
collaborating with Enigma on reference designs, including Bay Micro, Greenfield,
and EZ Chip.
Enigma's Switch Fabric breaks with the shared memory
architecture that's been almost universally used till now and introduced
a true 36 x 36 crossbar system (see Fig. 2). This allows it to switch full-sized
variable length packets in one go instead of breaking them down into fixed-length
cells like most other high-performance fabrics currently do it. I had some
concerns that the variable-length packet architecture raised the potential
for excessive latency variation within the fabric but, at least from my
quick scan of Enigma's white paper "HybriCore Architecture Quality
of Service" (available upon request), it looks like it's well-handled
between the priority mechanisms within the chip set and the tagging schemes
that support it.
Enigma claims that the switch's Byte Align scheduling
algorithm achieves 98% bandwidth efficiency by shipping packets across the
fabric in a back-to-back fashion with little or no wasted space between
them except for tagging overhead. I argued with Enigma's claim that fixed-length
switching architectures suffer from a 50% cell tax are a bit exaggerated
-- even in applications dominated by short packets. When pressed, they admitted
that typical overhead in fixed-length switches is probably more like 20%
- 30%. Nevertheless, Enigma's scheme allows you to wring much more usable
capacity out of the same amount of theoretical bandwidth.
And speaking of theoretical bandwidth, the current
chip sets' maximum capacity is 2 Tbit/s (full-duplex) in a non- redundant
configuration and 1 Tbit/s if a fully-redundant switching scheme is employed.
The current chip set cannot be expanded further through multi-stage meshes
but Enigma's plans include development of chips that will support this for
bigger fabrics.
The Fabric Manager interfaces the aforementioned
switch fabric via its SerDes connections and to your choice of packet processing
silicon via four SPI 4.2 links (see Fig. 3). Whatever processor you use must
be programmed to support Enigma's packet tagging scheme that defines 256
flows/stream per SPIE interface with eight classes of service. The Fabric
Manager generates a 2nd tag that's appended to the packet to supply port
destination, priority, and a four-byte CRC (the 2nd tag is stripped upon
egress).
The chip set has just
enough buffering (around 1Mbyte total, located in the Fabric Manager) to
handle the latency involved with its back-pressure throttling mechanism.
The remainder of the buffering tasks are left to whatever packet engine
you're using to drive it. Multicast replication is handled in two stages.
The 1st tier of multicast replication is performed within the fabric itself
to make the selected packets appear on the input of the appropriate Fabric
Manager egress ports. The Fabric Manager then handles the actual packet
duplication (see
Fig. 4).
Besides its memory-free crossbar architecture,
the most notable feature of the Enigma chip set is its high speed SerDes
links which uses technology licensed from Rambus. The transceivers support three different line coding schemes; a traditional
8B/10B NRZ format, a more efficient 64B/66B scheme, and a 4-PAM multi-level
signaling technique (licensed from QuickLogic) that uses Enigma's
proprietary (and patented) 16b/10b line code. Depending
on distance, channel conditions, and how much power you want to burn the
transceivers can support data rates between 2 Gbit/s and 12.5 Gbit/s.
To support the high speeds and the higher linearity
required by the multi-level coding scheme, the transceiver sports a 20-tap
DFE-based equalizer, plus programmable transmit pre-emphasis. Between the
DFE and PAM signaling, it looks as though Enigma has borrowed some of the
best ideas from Accelerant (reviewed here several times over the years), a pioneer in multi-Gigabit
SerDes technology which was acquired by Synopsys a year or so ago. Another
"fingerprint" that eerily echoes Accelerant's technology is its
low-bandwidth in-band back channel signaling scheme that the transmit and
receive sections use to communicate with each other and continuously tune
themselves to changes in channel conditions. Designers will also appreciate
the device's programmable slicer levels and on-chip BER logic that allows
you to determine receive signal eye size. The transceiver's post-EQ tap enables you to
see the received signal as the CDR sees it.
The EN6240, Enigma's largest Fabric Manager device,
has 14 bi-directional SerDes links. Any of these links can be configured to serve as a control plane channel to
configure the manager's response to tags, buffer watermarks and multicast
behavior. The Fabric Manager's embedded processor
core/state machine manages the control links and provides a user interface
that enables users to adjust settings and collect traffic statistics.
While I think that Enigma may have a real winner here, I feel obligated to
take a reality check on the performance claims they make for their SerDes
links. After having some hands-on experience with 2.5 - 5Gbit/s SerDes
silicon running in several typical (is there such a thing?) copper backplane
environments, I know that there can be a pretty large gap between a
product's theoretical performance and what it does under real-world
conditions. Having seen how channel impairments, reflections, and crosstalk
affect a transceiver's reach and overall performance at these lower speeds,
I must wonder how far, exactly, and under what conditions Enigma expects to
achieve 10 Gbit/s and even 12.5 Gbit/s.
Granted, the 20-tap DFE will do wonders for correcting
extreme non-linear attenuation but I'd have to see an operating backplane
system for myself before I felt confident in this chip set's ability to
reach more than 12 inches - 24 inches at speeds above 6 - 7 Gbit/s without
having to resort to exotic backplane materials or fabrication techniques.
My experience also shows that some of the worst problems occur in very short
reaches where reflected energy raises all sorts of havoc with the received
signals. In this case, I believe Enigma's closed-loop adaptive control would
help minimize problems, but I'd be much more comfortable with some actual
data and scope shots of working silicon.
Of course the field is not completely free from
competition. Besides the ASICs that larger companies still tend to prefer
for their high-end boxes, Enigma must face down switch silicon from Sandburst
(recently acquired by Broadcom) and Dune (which is strategically tied to
Marvell). Dune integrates a traffic manger into its switch -- a feature
that's good for lower-end applications where flexibility is not critical,
but you are locked into what Dune considered essential unless you want to
disable the manager and add your own silicon. This is a do-able, but more
expensive option because you still need to provide the switch with external
buffer RAM.
Back in the pre-2001 era, it was rather common
to find a networking-oriented semiconductor company like Enigma whose first
product had such an ambitious design, gate count and market strategy, but
these days I can count the number of feisty start-ups like this I see in
a year on one hand. The relative scarcity of these kinds of ventures is
mostly due to today's tougher economic conditions which dictate they must
actually sell a reasonable number of chips before they enjoy the inevitable
sell-out to Broadcom, Marvell, PMC, or one of the other big-time chip makers.
This in turn requires something more than a me-too product that actually
works and addresses a market segment that actually exists. Enigma's scalable
high-capacity switch fabric seems to fit most of these criteria and, while
some questions still remain about a few of its operational details, may
be well-positioned to sell chips to a variety of bandwidth-hungry applications.
The unknowns about the chip set's SerDes links
add at least a half-saltshaker to Enigma's Vapor Index rating. But, if the
transceivers can come close to what's claimed for them, they have a good
shot at selling a lot of chips.
All the parts are sampling with pricing for the
Enigma Fabric Manager ranges from $280 for the 3-link, 6.25 Gbit/s EN6210
to $700 for the 14-link 10 Gbit/s EN6240A, and for the Enigma Switch Fabric
ranges from $350 for the 18-link EN6105 to $625 for the 36-link EN6110A.
Product Brief
analogZONE
(c) 2006. All rights reserved.
The chip set consists
of a Fabric Manager and a Switch Fabric that are linked by a series of high-speed
(6.25 - 12 Gbit/s) SerDes channels. It is a pure switch device and relies
on external traffic managers and NPUs to perform classification, queuing
scheduling, and packet processing tasks (see Fig. 1). As we'll see shortly,
the Fabric Manager's generic SPI 4.2 interface makes it easy to use with
most third-party silicon, allowing designers to mix-and-match a system to
their needs rather than relying on a canned solution. Its open architecture
has also allowed this relatively small chip maker to enjoy an unusually
large ready-made ecosystem of first-line networking silicon to play with.
In fact, several of my favorite packet processing silicon makers are already
collaborating with Enigma on reference designs, including Bay Micro, Greenfield,
and EZ Chip.
