networkZONE Products for the week of May 20, 2002
The Scimitar AZ61100 integrated circuit is the industry's first single-chip, 5 Gbps open architecture solution that simultaneously performs the dual roles of traffic manager and ATM SAR on the optical networking line card. Managing as many as one million active traffic flows, Scimitar AZ61100 provides the most accurate shaping, policing, queuing, scheduling, and congestion management of any traffic management solution on the market. It also offers the highest density and lowest power consumption. This unique combination of industry firsts enables Azanda's OEM customers to deliver the next level of performance, port density and service features, while guaranteeing that Quality of Service (QoS) is maintained across the line card for a rich set of ATM and packet-based service classes.
Scimitar's Cutting-Edge Solution for the OEM Dilemma
Today's service providers are caught between two competing needs - to reduce
CAPEX by leveraging existing equipment, while still deploying new services
and better QoS in their networks in order to generate incremental revenue.
Scimitar's attributes are based on the premise that network OEMs recognize
the network processor (NPU) cannot, by itself, perform all functions required
by high-speed networking systems at line rate. As a result, there is significant
demand for additional application-specific silicon to augment the NPU's
capabilities. Scimitar AZ61100 was designed specifically to resolve the
OEM's dilemma with an evolutionary open architecture that gives service
providers and carriers the ability to take advantage of their existing infrastructure.
"The fact that Scimitar AZ61100's open architecture supports not only next-generation multi-service platforms, but legacy ones as well, makes it particularly attractive to our Tier 1 customers," said Bidyut Parruck, chief technology officer and founder of Azanda Network Devices. "Currently, our network OEM customers are not looking to make massive investments into completely new architectures, but to leverage their existing investment in network processors and switch fabrics. As a result, we foresee Scimitar technology cutting a wide swath across the market for merchant silicon in router and switch networking systems, as demand reemerges for enhanced services requiring sophisticated QoS."
With Scimitar AZ61100, OEM customers can scale the capabilities of their existing routing and switching platforms, without reengineering their network processor and/or switch fabric architectures. Scimitar augments the existing packet-processing capacity of the OEM's current NPU by off-loading the processing-intensive functions to achieve sophisticated, fine-grained QoS. Scimitar's configurable yet deterministic traffic management engines elegantly complement the programmability of the NPU by delivering QoS features required by next-generation platforms at wire speed. This combination preserves the OEM's significant investment in millions of lines of NPU code while scaling the line card to the next level of performance, port density and feature set. Moreover, Scimitar's evolutionary open architecture and industry-standard interfaces such as PoS-Phy Level 3 and SPI4.2 seamlessly interoperate with NPU datapath interfaces, accelerating an OEM's development process, and enabling quicker time to market for line card upgrades into existing chassis platforms.
Thanks to Scimitar's configurable shaping, scheduling and tunneling features, service providers can traffic-engineer their legacy network infrastructure to deliver advanced new services such as virtual private networks (VPNs) and packet-based real-time service level agreements (SLAs). But regardless of the features configured, Scimitar's deterministic hardwired algorithms deliver wire-speed performance, providing a natural complement to a programmable packet processor.
In order to meet this OEM demand and achieve Scimitar AZ61100's bandwidth density of 5 Gbps in a 40 mm x 40 mm Flip-Chip Ball Gate Array (FCBGA) device, ultra accuracy of better than 100 ppm, and low power consumption of less than 5 watts, Azanda utilized 10 Gbps technology to develop a highly integrated OC-48 full-duplex traffic management solution.
Said Jag Bolaria, senior analyst with industry research firm The Linley Group, "Azanda's use of its 10 gig technology to power its full-duplex OC-48 product delivers breakthrough traffic management density. Scimitar's power and external memory component count is significantly lower than today's leading OC-48 traffic managers."
Single Chip, Multiple Functions
Though just a single piece of silicon, Scimitar AZ61100 can perform all
traffic management functions on the line card. Sitting on the fabric side
of the line card, Scimitar AZ61100 performs both ingress and egress traffic
management into the systems. While on the line side next to the framer,
it performs ATM segmentation and re-assembly and ATM/MPLS lookup and header
processing.
Azanda also offers a complete Scimitar software development environment that enables fast time to market of a full-featured wire-speed OC-48 router and switch line cards. The Azanda API makes it easy for OEMs to integrate their existing code to work with the Scimitar environment. Azanda's Scimitar AZ61100 is also OS "agnostic" and features a configurable hardware-based design implementation.
Additional Features of Scimitar AZ61100:
analogZONE Says . . .
Any Way You Want It - Azanda's Scimitar Manages ATM & Packet Traffic At Full-Duplex OC-48
I'm very impressed with Azanda Network Devices' Scimitar, a full-duplex traffic manager and ATM SAR targeted for carrier-class OC-48 applications. It's interesting to note that their design was originally targeted for OC-192, but Azanda had the good foresight to re-spin the design to hit the more mature (read actually shipping) OC-48 market. With some of the guts over-designed for the faster speed, I'll guess that there is sufficient margin for this chip to actually perform as-advertised.
Azanda's re-targeting for the OC-48 markets is one of three or four important trends that they managed to track that position it very well to win sockets in the equipment that will be shipping in volume this coming year. Besides departing from the stampede to CO-192 and concentrating on the reality of OC-48, Azanda is both lucky and smart to have understood the need for stand-alone traffic managers in the days when NPUs were being touted as one-chip-does-it-all products. Finally, their ATM capability and protocol-agnostic architecture makes it easy to do adjust to the reality that the TDM-based carrier infrastructures of the incumbents are going to be with us for some time to come.
The Scimitar contains several architectural elements that should make this chip a winner in today's brave new environment. First, to deliver the deterministic performance (uniform latency) that TDM and other multimedia applications demand, they chose to use a configurable state machine architecture, rather than the cluster of programmable RISC machines that are the fashion today.
Using configurable state machines has some downsides - i.e. you can only invoke existing functions and features. In other words, if you have some hot new queuing algorithm you want to implement, you'd best find another machine. If, on the other hand, you want to use virtually any combination of existing queuing schemes (RED, WRED, WFQ, WRR, etc…), and other traffic management tools, you can easily configure the chip via the control plane processor interface (a generic 32-bit interface similar to MIPS bus). Multiple schemes can be concatenated and configured at will without jeopardizing the throughput of the device. This very straightforward way of setting up queues and queuing schemes allows the bulk of your software development efforts to be concentrated on the NPU.
The Scimitar sports three full-duplex interfaces that can be used simultaneously. The first two are POS-PHY-3s, plus a SPI-4.2. Most customers use the two POS-PHY L3 interfaces to perform either "fabric side" traffic management (the chip sits between NPU and fabric), or "line side" management, which allows the chip to do ATM processing before the traffic hits the NPU.
Some customers however, attach a "recirculating" look-aside function to the SPI-4.2 port. They can use it to push selected data up to a classifier or encryption engine, and then re-introduce the processed stream back into the manager's original data flow. With the intelligence offered by some of the more advanced classification engines, such as the FastChip PolicyEdge chip I recently reviewed<Please INSERT LINK TO http://www.chipcenter.com/networking/products_200-299/prod248a.html>, you can probably replace the NPU in many applications. In fact, Azanda has recently signed an agreement with FastChips for interoperable classification and tagging. This lets the Scimitar perform traffic scheduling and shaping based on the tagging provided by the PolicyEdge.
The chip's internal data flow is also somewhat unique for a packet processor. Any traffic (packets, cells, or whatever) entering the chip is run through an internal SAR that breaks up packets up into ATM-sized cells before storing them in memory. This allows the Scimitar to support multi-service traffic, and be equally comfortable with cells and packets.
With an architecture built around shuffling uniform-sized cells, the chip can be made to deliver the deterministic characteristics that facilitate internetworking between IP and TDM-based systems. This, and the built-in SAR logic makes it a good candidate for aggregation and traffic management at WAN's edge where IP traffic from ISPs meets metro SONET rings and in DSLAMS where ATM is used to encapsulate, transport, and manage traffic on its way to the CO.
Internetworking also demands that the chip be "packet-aware." In other words, it must be smart enough to know to drop the entire packet when a single cell is lost. Conversely, it must do traffic shaping on a per-packet basis, holding all relevant cells that make up a given frame during buffering and scheduling operations. If you're handling ATM traffic, you can invoke other modes for part, or all of the data flow that can do traffic mgmt on a hard per-cell basis.
This positions Azanda's chip to find homes in boxes designed to work with the enormous amount of legacy ATM equipment found in the cores of most incumbent carriers, as well as the surprising number of next-generation ATM equipment in that is currently in the design phase.
Another thing that tells me these folks are pretty good at delivering on their promises is the story that Greg Wolfson, Vice President of Marketing at Azanda told me. He said that they hand-carried the first Rev 0 silicon back from Taiwan the day before N+I and then got it up and running for customer demos by Wednesday morning. Given the complexity of the chip, and the amount of high-speed mixed-signal circuitry on board, I'm impressed. Greg explained that a good part of their success this spring is due to the test silicon they spun in October, which uncovered many issues with the SPI-4.2 and POS-PHY interfaces. The test chip was specifically designed to explore the characteristics of the analog circuits, PLLs, VCOs, and all I/O they were using.
I have only two concerns with this chip. First, I think that it may be "too much silicon" for many applications. Many potential customers probably find that large parts of the chip such as the SAR functions, parts of the policing & management algorithms, and perhaps one of the ports is not going to be used in many applications. Maybe this is being picky though, because, even with all the bells and whistles, the dedicated logic still probably takes up a smaller amount of gates and silicon real estate for a CPU-based programmable solution with equivalent capabilities. I'd also quibble with a price tag of $1000 as being a bit steep. But I guess that the marketing department knows a) the value of the many chips the Scimitar will replace in most applications, and b) how much lower the street price will end up being when significant production volumes are involved.
The Scimitar AZ61100 is selectively sampling this month with production scheduled for the fourth quarter, priced below $1000 per device in volume quantities.
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