networkZONE Products for the week of May 10, 2004

Galazar Networks Says . . .
Revolution-on-a-Chip: Galazar's Multi-Protocol Adapter Enables Ethernet-over-SONET/SDH, UPSR, and RPR Rings With Layer 2 Packet Processing
New VersaNode product portfolio addition supports high-touch packet processing and multiple metro access network architectures

Galazar Networks Inc. has introduced VersaNode, an OC-12/3 Multi-Service versatile networking solution for Ethernet and PDH services over point-to-point networks, RPR and UPSR rings. VersaNode expands Galazar's existing, successful product family of PDH and Ethernet over SONET/SDH (EoS) multi-service framers. VersaNode is ideal for multi-service line cards and customer premise equipment access platforms that are designed to support ring and hub-and-spoke network topologies with distributed layer-2 packet processing over mixed High Order (STS/VC paths) and Low Order (VT/VC paths) Virtual Concatenation (VCAT) groups with Link Capacity Adjustment Scheme (LCAS).

"With carriers focused on deploying new, revenue generating services over the existing SONET/SDH network, equipment vendors are working closely with Galazar to extend their success in Ethernet over SONET (EoS) into improved packet aggregation technologies and enhanced packet processing services," said Richard Deboer, CEO, Galazar Networks. "VersaNode enables our customers to offer additional layer 2 services and network architectures while leveraging their investments across a common hardware and software platform for universal line cards capable of supporting GFP, mixed High Order VCAT and Low Order VCAT with LCAS."

VersaNode's target applications include multi service cards for SONET/SDH ADMs, MSTPs, CPE/CLE terminals or Metro Core switches. Galazar's new VersaNode was designed to target multi-service applications that require enhanced packet processing abilities such as Packet Rings (e.g. RPR and VT), Class of Service (CoS), VLAN segmentation and other value added data services.

Galazar's framers are the world's first devices to simultaneously support mixed High Order (STS/VC paths) and Low Order (VT/VC paths) Virtual Concatenation (VCAT) with LCAS. These features increase a carrier's service offerings and revenues from the existing infrastructure.

analogZONE Says . . .

For a relatively small startup company, Galazar has had a disproportionately large impact on the somewhat staid SONET world. In the past couple of years, they have introduced a number of pioneering multi-service and SAN-over SONET devices. They've also been extremely active in the development of LCAS, VCAT, and other critical extensions of the SONET standard that support modern packet-oriented services. Their new VersaNode device goes even further realizing their vision of flexible, bandwidth-efficient, any path/any service connections over existing TDM networks.

While their earlier products combined multiple mapping functions into their silicon, VersaNode goes one step further. This beast integrates a complete set of network elements to support multiple network architectures on a single chip.

As the block diagram will attest, this chip literally bristles with subscriber-side interfaces that support most common communication protocols (other than Token Ring and Teletype). You can seamlessly connect Ethernet (8 10/100 and 2 GigE ports), TDM voice or data (28 DS1/E1s and 3 DS3/E3s), or telecom traffic (via the 155/622 Mbit/s TDM telecom bus). If you need to terminate Frame Relay or ATM traffic (or some other format for that matter), you can add an external mapper. The line side of the device is a nice, straightforward OC-3/12 (or STM-1/4) SONET interface, with the obligatory TOH/POH insert/extract ports to allow add-drop functionality. Galazar's nifty internal time slot assigner (TSA) replaces the traditional ADM logic and still lets framer pick off any time slot within a SONET frame.

So how do all these features play together? Hold on tight and I'll try to give you a few examples of what you can do with VersaNode. Its on-chip Ethernet MACs can steer IP traffic directly to the framer for simple point-to-point or backhaul EoS connections across your favorite WAN. You also get the option of taking traffic out through a coprocessor port (via a SPI-3 interface) that can take Ethernet traffic outside chip for additional processing. While you can go up through L7, Galazar anticipates most processing operations will be at L2/3 to do tagging (for aggregation) classification (priority control), and implementation of new services such as Resilient Packet Ring (RPR).

This external processing allows carriers to add value to their services by providing additional features and functions. You can easily perform classification and separation of traffic into different VC groups with different priorities before the traffic hits the WAN. External processing will also enable a single EoS connection to simultaneously support VoIP and data traffic. Broadband service providers will also appreciate the ability to do stat-muxed traffic aggregation for efficient, transparent over subscription.

One of the most interesting things that you can do with this outboard processing capability is to attach an RPR MAC -- either using an FPGA, dedicated silicon, or a network processor of your choice. This would enable a single blade or small CPE box to provide both high- and low-order mapping for provisioning RPR services and make it possible to deploy new RPR-based services at a low price point.

I suspect Galazar's already working on a merchant chip to support RPR or some of the other more popular packet processing options, if an enterprising designer was in a hurry, they could spin their own ASIC or burn an FPGA right now. In fact Galazar is already in discussion with Xilinx on developing some FPGA-based reference designs to support advanced services. I also pointed out that the VersaNode is a good candidate to be teamed with Seaway's powerful content-oriented packet processor. I reviewed the SW5000 last year and was so impressed with its ability to look deeply into packets at any layer that they received one of analogZONE's Product of the Year awards.

So, is this a RoC (revolution on a chip) product? Maybe. Given the strong interest in supporting new services on existing SONET/SDH infrastructures, and the promise of RPR, Galazar's VersaNode may well be the product that pushes these trends past the tipping point by making it sufficiently easy and inexpensive to deploy.

If this does happen, you can expect to see lots of Galazar silicon appearing in multi-service transport platforms MSTPs (Cisco 15454 equivalents) and multi-service switching platforms (MSSP) which have SONET/SDH interfaces, but don't have framing capabilities. You'll also see the VersaNode on multi-service cards with plug-ins that will add EoS RPR, or other WAN services a traditional blade-based networking box.

And Galazar seems to be greasing the way towards that tipping point by making development as easy as possible. They're developing some management software in parallel with the chip that goes far beyond simple drivers and provides the key ingredients for reference designs that support many different service models. They are also trying to create complete "solution sets" that include the chip, an evaluation board, associated management and application software, plus reference designs that include 3rd-party ICs and software. Given their previous track record, I expect that we'll see at least 80% of this collateral material arriving when the chips come to the general market in early 2005.

The chip is in the final stages of design, with the support code and evaluation system in a parallel development effort. It will be fabricated in a standard 0.13 micron CMOS process and is expected to consume 3 - 4 W, depending on the speed it is run at.

The Galazar VersaNode will be Alpha sampling to selected customers in Q4 2004. It will be available to general customers in Q1 2005. Disappointingly, Galazar is being coy about pricing, indicating that there will be several different application-based pricing schemes that vary depending on bandwidth and value of the intended application.

Data Sheet

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