networkZONE Products for the week of May 10, 2004
Erlang Technology Says…
Erlang's Protocol-Agnostic Scalable Switch Fabric
Chipset May Make You A Believer
Variable-Length Packet Processing Architecture works with
Leading NPUs, Boasts One Tbit/s Scalability for Communications, Wireless
and Storage Routing and Switching Equipment
Erlang Technology, Inc. announced the availability of its new flagship
switch fabric chipset boasting the fastest scalability, shorter time-to-market
and other benefits that make it ideal for a myriad of routing and switching
applications in the communications, wireless and storage markets. The Erlang
Network Element Technology (ENET) Xe chipset is the company's second generation
ASIC-based switch fabric chipset. A non-blocking switch fabric, the ENET
Xe enables the fastest scalability to one terabit per second, supports variable-length
packets and much more, making it ideal for interfacing to multi-vendor traffic
managers, network processors (NPU) and in-house ASIC implementations.
The ENET Xe's non-blocking and variable-length packet processing features overcome scalability bottlenecks that exist in conventional output buffered switch fabrics while requiring no off-chip memory. The Xe can process variable-length packets from one byte to 16 KB. The Xe also incorporates industry-standardized interfaces such as CSIX-L1, L3, NPSI, POS-PHY, SPI-3 and SPI-4 to seamlessly interface to merchant NPUs from vendors such as Agere Systems, AMCC, Intel and Motorola. In the end, the Xe provides a flexible, reliable and cost-effective switch fabric solution for high capacity switch and router systems requiring fast and seamless scalability up to one Tb/s.
The Xe chipset is protocol independent, supporting all types of traffic, from IP and ATM to TDM and Ethernet traffic, and provides sophisticated support for QoS through Erlang's proprietary Train-Queuing technique. Other service features include support for Multicasting, Broadcasting, Strict Priority and Weighted Fair Queue scheduling, and High Availability.
A system built with the ENET Xe consists of two devices, the XeI for interposer and the XeC for the switching core. As the two chips interface to each other through a high speed XAUI interface, fewer links are needed to communicate with each other compared to competitive solutions. The XeC can be configured to operate in three modes: Ingress Queue Manager Mode, Core Switch Mode, and Egress Queue Manager Mode. The XeI is a 10 Gb/s full duplex interposer device that supports up to four 2.5 Gb/s NPUs for full-duplex traffic. It can also perform as a single-chip 4 x 2.5 Gb/s switch fabric, while providing excellent QoS support. The XeI is the data and control path glue between an NPU and the XeC.
A 10 Gb/s version of XeI will connect to popular 10 Gb/s NPUs through an SPI-4 interface. The interface between the XeI and XeC occurs via multiple 3.125 Gb/s high speed serial links, which are also used between multiple XeC devices.
"The ENET Xe is the pinnacle of more than 10 years of switch fabric chipset design and several design wins behind Erlang Technology," said Dr. Paul Min, CEO of Erlang Technology. "The fruits of our labor are evident in the excellent features the Xe brings to market. The Xe boasts excellent forward-thinking features such as handling packet sizes from one to 16 kilobytes for greater use in applications with different NPUs and traffic managers, and also in systems addressing the Resilient Packet Protocol (RPR). We also optimized the queuing by handling internal transfers at 32 byte granularity, as well as many other advanced capabilities. We're confident the Xe will exceed the cost, performance and integration needs of our customers worldwide."
Erlang Switch Fabric Market Needs and Applications
A host of network equipment manufacturers (NEM) that provide products such
as access and edge routers, enterprise backbone switches, core routers and
multi-service platforms will find Erlang's Xe chipset an ideal fit for manufacturing
cost effective, highly scalable and reliable equipment. Manufacturers of
wireless routing and switching equipment will also find Erlang chipsets
ideal for gear such as 3G wireless gateways and base stations. And storage
area network (SAN) equipment vendors will benefit from Erlang's product
in devices requiring 320 Gb/s throughput and upwards for their backplane.
WinterGreen Research, a market research firm, estimates that by 2009 switch fabrics will grow to be more than five times the market it was in 2003. The Linley Group, another market research firm, predicts "a major platform upgrade cycle" to begin to take hold in 2004 leading to increased market size for switch fabric chip vendors. Market research firm Electronics.ca chimed in on the prospects of a healthy market for switch fabrics stating in an August 2003 market research report, "We are entering a period when several forces should combine for this market to experience healthy growth for the next five years."
Erlang Technology, now an established player with several design wins and second generation products shipping, is well positioned to take advantage of this market growth with high-performance switch fabric and hardware-based content search engines that provide two to four times the capacity, the highest scalability available, and superior QoS performance. In order to speed up time-to-market for NEMs, Erlang provides pre-engineered, complete system solutions consisting of switch fabric chipsets that seamlessly integrate with leading NPUs, communication processors, CPUs, and DSPs. In addition to the traditional network telecommunications market, Erlang has a presence in several market segments of the wireless and storage network markets.
"Erlang Technology has tremendous system design knowledge," commented Suneel Rajpal, VP of Marketing and Sales, Erlang Technology. "The Xe chipset is available with proven reference designs using the Intel IXP2400 and, IXP2800 network processors, as well as Motorola's C-5e network processors and Agere Systems' APP5X0 and PayloadPlus NPUs."
At 156 MHz, the ENET Xe also boasts the lowest clock rate of any switch
fabric, which minimizes power dissipation and eases system integration.
The Erlang ENET Xe is fabricated using a 0.15um process technology from
NEC Electronics.
analogZONE Says . . .
When Colin Mick first sat down and explained the goals of the newly-formed CSIX (Common Switch Interface) Consortium back in 2000, he said that by providing a standard connection between network processors and switch fabrics would promote innovation and drive down the cost of IP processing. And although the tech implosion of 2001 did delay the full realization of this dream, the introduction of Erlang's most recent family of switch fabric products is living proof that Colin was right. I say that this is their most recent development because although the ENET Xe is their first commercial release, the design team has three earlier generations of chips under their belt from the time they spent at Washington University beginning in 1993. But, getting back to the present, their new chip set looks to be a highly cost-effective switch solution that could find its way into many applications because of its high performance and its ability to "play well with others".
The current offerings consist of the XeC, an 80 Gbit/s (full duplex) switch fabric chip, and a family of different "interposers." These interposers sit on a line card between a network processor, or other line-side devices, and a serial backplane connection. Their job is to packetize the data, schedule it according to the tagging generated by the upstream NP or classifier, and then pass it on across the backplane to the switch fabric.
The ENET-SeI-CSIX is a CSIX-compliant interposer that presents a "generic" interface for use with any other CSIX-capable NPU or packet processing device. The XeI model interposer presents a quad 2.5-Gbit/s XAUI interface that supports most OC-48 NPUs including the Agere Payload Plus, Intel's IXP, and Motorola's C5 series, as well as many other traffic managers or classification devices. A 10 Gbit/s, OC-192-capable interposer will be introduced later this year.
All devices communicate with each other via on-chip 3.125 Gbit/s SerDes links (IP cores licensed from NEC) that allow for a low interconnect count. Erlang says that the SerDes' programmable pre-emphasis and simple receive equalizer circuits allows reliable links of up to 30 inches of standard FR-4 PCB material.
Each XeC fabric chip connects up to eight 10-Gbit/s interposers, giving it 80 Gbit/s of capacity. You can create a mesh structure that scales up to 640 Gbit/s. And since each interposer has two sets of SerDes ports, you can easily build a redundant mesh system for mission-critical enterprise or carrier-grade applications.
Like some of its competitors, the Erlang's switch fabric uses a cell-switched architecture (over shared memory) which handles any payload as a series of fixed-length (32-byte) cells for transport across the fabric. Using fixed-length cells enables it to shove data between ports in a very deterministic way, making it much easier to enforce strict QoS than a packet-switched architecture. Since much of basic flow control is already handled by the time slotting in the fabric, there's much less control logic required in line cards -- a nice side benefit that minimizes repeated scaling costs. Erlang says that the short 32-byte cells it uses are extremely efficient because you're sending out fewer partially-filled cells. Although I might dispute this because of the additional tagging overhead, the extra 2 bytes might be a small price to pay for being able to meter out bandwidth with such fine granularity.
Although a shared memory is the most common architecture used for switches these days, there are several important features that keep this from being simply a "me-too" product. Perhaps the most noticeable difference from other shared-memory fabrics is that the switch fabric has 6 Mbyte of on-chip memory and does not require any external RAM. This allows the switch to support up to 576 flows and up to 264 queues per port while applying WRR, WRED, deficit WRR, or strict priority queuing on a per-flow basis.
Thanks to some very efficient queue-loading algorithms that take advantage of the deterministic cell switching scheme to carefully dole out memory the fabric is non-blocking even when run at full rate on all ports. Each interposer also has 2 Mbyte of internal RAM (for output queuing) that is used to increase the number of queues and flows. Eliminating the external RAM on both the line and switch cards provides big cost and power savings, not to mention a big speed advantage.
Of course, even with the power savings realized from eliminating the memory interfaces these chips are large and draw some significant power. Power consumption for the XeC switch fabric is 19 W, and 7 W for the XeI.
The switch supports both virtual output queues (at the input port) as well as a set of virtual input queues (at the egress side). Besides allowing for much more granularity and control of flows, it supports a unique backpressure mechanism which only signals the source which is creating an overload condition. Erlang's control scheme allows a single port to back down its rate while the other sources are unaffected. This is in contrast to most switch architectures that broadcast a backpressure message to all ports. Here it only slows down the distressed port.
The chip set's cell-based architecture is protocol-agnostic and equally happy moving ATM, IP/Ethernet, SONET, PoS (up to 9 kbyte), and other, fixed or variable-length traffic. This means that you can even mix-and-match traffic within the system, opening up some very interesting possibilities for developing true multi-service products as well as more conventional low- and mid-level IP switches that efficiently support data and VoIP traffic. The scalable (80-640+ Gbit/s) fabric should find homes in environments as diverse as wireless, enterprise, and even core IP, SONET, and RPR networks.
Erlang also makes the intriguing claim that their switch architecture can be easily adapted to switch serial interconnect traffic, including serial RapidIO and Intel's Advanced Switching protocols. They are currently working on another "flavor" of the chip set that should find lots of applications tying together large Advanced TCA systems and wireless infrastructure applications.
Of course, this is a very competitive market these days, with several other excellent switching solutions being rolled out this month -- including the teaming of Xelerated's extraordinary pipeline NP and Broadcom's upgraded StrataSwitch chips I'll be reviewing next week. With so much at stake, part of Erlang's strategy to take on the "big boys" is to make product development extremely quick and easy. That's why they are providing complete implementation support to customers, including design services. They can even provide pre-engineered designs that interface to several NPs and licensable reference designs. And if that's not quick enough for you, they also offer board-level products that can be used to jump-start for small volume runs to help you "get your feet wet."
I have not had the time to run the numbers on a typical application, but given the fact that this chip set requires an external NPU for every 10G connection, I suspect it's got a slightly higher cost-per-port than, say the Greenfield solution I recently reviewed. On the other hand, the high level of flexibility and protocol-agnostic traffic capability that the Erlang chip set offers may well make up for this in many applications.
The availability of silicon and the earlier history of successful products earn Earlang a reasonably low Vapor Index Rating, despite some sketchy information about a few architectural details.
The ENET Xe chipset is sampling with the XeI priced at $400 and the XeC priced at $495, both for 5-k piece lots.
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