networkZONE Products for the week of May 6, 2002
The price-performance and programming ease of Intrinsity's FastMATH microprocessor improves the economics and time-to-market schedules of many application areas, including medical imaging, military systems, network infrastructure and mobile data communications. Designed to scale beyond 4 GHz, the FastMATH processor delivers six times the performance of the fastest DSPs on common, math-intensive operations, such as the Fast Fourier Transform (FFT) algorithm. Adaptive signal processing algorithms are even more math-intensive and must quickly compute new system parameters based on multiple high-speed data streams.
"DSPs, FPGAs and desktop processors are clearly not meeting all the needs of today's high-performance adaptive signal processing applications. Intrinsity is utilizing its patented design technology, Fast14 Technology, to create very high performance processors that will help our customers accelerate the wide-spread adoption of these applications," stated Paul Nixon, CEO, president and co-founder of Intrinsity. "Our FastMATH Adaptive Signal Processor product can provide the computational speed of ASICs, while delivering the well-proven cost and time-to-market benefits of industry-standard RISC microprocessors."
Adaptive signal processing systems typically consist of arrays of changing data that require complex processing to deliver real-time performance in response to changing conditions. Broadly-defined examples include picking signals out of background noise, canceling out interference from multiple sources and dynamically altering systems to respond to inputs from sensors or data streams. A large number of well-established adaptive signal processing algorithms already demand either higher computation rates or lower-cost implementations - or both.
2 GHz Matrix and Parallel Vector Math Unit - Provides exceptional parallel data computational performance on the commonly-used matrix and vector math data types found in adaptive algorithms.2 GHz MIPS32 Architecture-Based Processing Core - Provides the ease of programming and flexibility to address changing algorithms and standards.
High-Speed I/O - Allows complex, adaptive algorithms to be partitioned cost-effectively across multiple FastMATH processors by providing dual RapidIO ports. For the first time, these elements are combined to form an Adaptive Signal Processor chip capable of delivering unprecedented programmable performance in real-time signal processing applications. This technology is especially valuable to designers of wireless systems as they innovate new ways to extend the capacity of cell towers in wireless systems: "As more users crowd the usable radio spectrum and demand higher data rates, more complex processing is required to make efficient use of this limited resource," stated Dr. Jim Gunn, Forward Concepts Senior consultant. "By accelerating adaptive signal processing algorithms with their multi-GHz FastMATH processor, Intrinsity offers technology that can enable wireless systems to make more efficient use of the limited bandwidth available for each cell site."
Intrinsity also announced the 2 GHz FastMIPS high-performance MIPS-based embedded processor. Delivered from a standard 0.13 µm foundry process and scaleable to 4 GHz, the FastMIPS product benefits from Intrinsity's Fast14 technology to allow multi-GHz performance without exotic manufacturing techniques. Targeted at high-performance embedded applications, the FastMIPS product also includes dual-RapidIOports to enable balanced system performance.
Intrinsity is a MIPS architecture licensee, and the FastMATH and FastMIPS processors are based on the MIPS32 ISA. The selection of the MIPS architecture makes designs easy-to-implement, allowing customers to leverage best-of-breed design tools from suppliers such as Corelis, Green Hills Software, HelloSoft, OSE Systems and WindRiver.
"We're pleased that Intrinsity has chosen the MIPS architecture
as the basis for its adaptive signal processing strategy," said John
Bourgoin, chairman and CEO of MIPS Technologies. "The replacement of
hard-wired logic and special-purpose processors by high-performance, general-purpose
processors has great benefit to SOC designers and is a trend we expect to
see increase in the future. "Intrinsity will begin sampling its FastMATH
and FastMIPS processors in 4Q 2002. Additional details will be disclosed
at the Embedded Processor Forum that begins on April 29, 2002. Complete
product specifications are available with the completion of a non-disclosure
agreement.
analogZONE Says . . .
Transforms 'R Us- Intrinsity 2-GHz Fast Math Embedded Signal Processor Is Optimized For Wireless
Talk about cramming 10 pounds of expectations in a 1-pound can! Intrinsity certainly seems to have done this when they announced their chip that combines a 2+ GHz embedded DSP, and its companion RISC controller a couple of weeks ago. They have ambitions to deliver a serious challenge to TI's and ADI's lock on high-performance signal processing in the wireless arena by offering products that offer better algorithmic support, as well as run a whole lot faster - in fact, many times faster than any existing signal processing chip.
Claims like those being made by Intrinsity would be hard to take seriously, except that they have working test chips (not the whole processor) that at least validate their "Fast14" design technology. The Fast14 transistor structure allowed a test chip made in standard 0.18-micron CMOS to run at 2.2 GHz. This gives me reason to at least hope they will deliver on their promise to have early silicon some time in Q4 '02.
To clarify a bit, their Fast14 technology consists of several elements. The first part is a proprietary transistor geometry and layout that they claim gives a 3-5X speed improvement over competing design methods - (Reality check: Analyst Linley Gwynapp says it will deliver at least 2X.) Fast14 also employs dynamic logic to achieve these speeds, plus a new clocking style that uses 4 overlapping clock phases per cycle. They say that this avoids the race conditions that plague higher speed dynamic logic.
While dynamic logic has been an academic curiosity for several decades, it is much more difficult to design with than static logic. That is, of course, unless you develop your own special design EDA tools to account for its peculiarities, something which Intrinsity has done. Among other niceties, the tool features "noise-aware routing" which performs trace placement that anticipates where crosstalk problems are likely to occur, and avoids them.
Tools like this allowed them to develop a new logic family that they call NDL (one of N dynamic logic.) The logic functions, which operate on 2 bits of information at a time, require fewer gate delays for a given function than standard binary logic. In addition to enabling rip-snorting processing capacity and curing male-pattern baldness, Intrinsity also claims that their technology can be coaxed to consume less power than competing dynamic logic implementations from Intel.
The first fruits of their efforts will be a pair of very fast processors sharing a single piece of silicon. Running at 2 GHz, the chip envisioned by Intrinsity will contain both a MIPS-like RISC CPU and powerful matrix math unit. Both are based on the MIPS architecture, but sport different architectural modes to make them more suited to their particular tasks.
Their FastMIPS CPU is an extremely hopped-up version of the venerable MIPS processor. While it is quite capable of all the standard control and compute functions performed by its slower cousins, it's primary job is to drive Intrinsity's FastMATH unit, a math engine that is optimized for matrix and vector calculations.
The FastMATH core programs a lot like a conventional external floating point unit (FPU) math co-processor used by MIPS machines in other applications. Data to be crunched is fed to the math engine via a 1-Meg L2 cache. An on-chip 2 port RapidIO interface connects the cache to the host, or to other Fast Math processors. An SDRAM controller and JTAG interface connect to the outside memory (up to a Gigabyte) to provide the math processor with a place to store variables and program data. Programming is downloaded from the FastMIPS via a MIPS standard coprocessor interface. Hooked in tandem, the awesome twosome runs TI benchmark FFTs 6X faster than TI's fastest 600 MHz 'C6x.
And, should you have really outrageous number crunching tasks to do, you can drive multiple FastMATH chips using a single FastMIPS processor.
When I asked what made Intrinsity different from the re-configurable processors offered by Chameleon and QuickSilver, they explained that it is fully programmable, rather than configurable. Although I'm somewhat algorithmically-challenged, their claim seems reasonable to me and that this would make it easier to easier implement new signal-processing schemes, especially ones that are adaptive in nature.
Today, adaptive algorithms are usually run on large arrays of DSPs in high-value signal-processing applications such as real-time MRI- and CAT-scan image analysis. Intrinsity is betting that if they could get the cost down, similar algorithms could be used to boost the capacity and quality of mobile/wireless communications. At least in theory, using adaptive processing to drive smart antennas and multi-user detectors can improve throughput by up to 3X.
These sorts of signal-processing tasks require fast matrix and vector operation capabilities to help them adapt quickly to fast-changing signals. Even Motorola's AltiVEC ,a very powerful and well-conceived hybrid processor, does not do these matrix operations. These capabilities could help wireless systems designers realize the long-promised "software radio" that can redirect its computing efforts to handle new or evolving standards in ways that ASIC- or FPGA-based systems won't.
Speaking of software, Intrinsity made a good decision in using the MIPS architecture as the basis for its product instead of something totally original. Basing their machine around a well-supported instruction set means you won't have to program this beastie with a handful of half-baked custom tools from the manufacturer. Instead, you'll have access to tons of software and software support from Wind River, OSE, Green Hills, MatLab, HelloSoft, and Corelis.
If Intrinsity hits its ambitious 4Q '02 sampling date with working silicon, I expect that it will find a home in places like wireless base stations - especially multi-protocol systems with extended capacity technologies. Should the 3G recover from its current stalled market conditions, this would be a good candidate chip for building base stations that could track the evolving standards and allow almost instant upgrades as new features, protocols, and maybe even modulation schemes arise.
With all the renewed interest in intelligence work, I also expect that it will find some military and "black" apps as well, in areas such as SIGINT and radar analysis.
As with anything that pushes several edges of the
envelope at once, I don't consider it a sure bet that Intrinsity will be
able to deliver on all its promises - even with the successful test silicon,
and the six-month lead time from their announcement. Nevertheless, their
validation of the technology with test chips and their use of the solid
MIPS architecture keeps my vapor index rating within (just barely) the credible
range. I'm rooting for the chip though, and look forward to hearing about
working samples some time before the snow flies this winter.
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