networkZONE Products for the week of April 25, 2005

Ample Communications Says…
All Muxed Up: Ample Communications' Smart MACs Enable Affordable VoIP Over Stat-Muxed GbE10G Advanced Priority Queuing Assures VoIP Quality of Service

Ample Communications has announced VoIP capabilities for its Harrier family of chips. Using Ample IQ technology in statistically multiplexed Gigabit Ethernet networks, the Harrier prioritizes voice traffic and sends it to the forwarding plane in a non-blocking fashion. This architecture allows voice traffic to get through 100% of the time to assure VoIP QoS. Additionally, Ample's statistical multiplexing capabilities enable 1 Gbit/s Ethernet deployment at 100 Mbps cost.

Ample's statistical multiplexing architecture prioritizes critical traffic, allowing traffic like VoIP to always get through before low priority traffic. Ample IQ enhances the statistical multiplexing capabilities in Harrier to ensure that VoIP is not affected in cases where traffic congestion occurs.

"Ample's ability to offer advanced priority queuing sets us apart from other chips on the market," said Ravi Sajwan, CTO of Ample Communications. "Our statistically multiplexed hardware differentiates high priority traffic, like voice, from low priority traffic. Using Ample's Harrier family of chips, enterprises and service providers can guarantee that voice traffic will get through 100% of the time, even in cases of network congestion."

The Ample IQ technology offloads network processors by preprocessing network traffic enabling the NPU to focus on application layer processing. By significantly reducing the processing requirements of communications systems, Ample makes intelligent gigabit links affordable at the edge.

Ample's Harrier has the added advantage that it is a family of devices consisting of three aggregation devices: Harrier-24 with 24 10/100/1000 Ethernet ports; Harrier-12 with 12 10/100/1000 Ethernet ports; and Harrier-24LS with 24 10/100 ports. Each device is software and pin compatible simplifying designs, reducing design time and reducing manufacturing costs. Each device interoperates with off-the-shelf Ethernet physical layer devices via standard RMII/RGMII interfaces and with off-the-shelf network processor units (NPUs) via a standard SPI-4.2 interface.

analogZONE Says . . .

Over the years I've observed that the most robust and scaleable systems are often the ones which push large chunks of their intelligence outwards to their edges. That's why I thought that Ample Communications' concept of doing intelligent congestion management at the MAC level made lots of sense when we first met at the Communication Design Conference last year. Unfortunately their news somehow got buried in the rush of all the other stuff coming out of the conference, and I never got around to writing about their clever approach to boosting the overall efficiency of Gigabit Ethernet systems. To correct this oversight, and by way of making amends, I'm using Ample's recent announcement about their ability to improve the efficiency of VoIP systems to belatedly call this unique MAC product to your attention.

Their Harrier 12- and 24-port MAC devices have been on the market for over a year now, but Ample has recently discovered that the device's ability to perform prioritized statistical multiplexing enables VoIP systems to intelligently oversubscribe their backhaul lines. Depending on the application you have in mind, Ample will supply you with 12 or 24 ports worth of Gigabit Ethernet GMII interfaces feeding a SPI 4.2 uplink interface, or 24 ports worth of 10/100 MIIs feeding a Gigabit Ethernet MAC (see Fig. 1). In their extreme configuration, they enable a 2.4x oversubscription without interfering with critical traffic.

They do this by providing two independent queues for each MAC port, a "fast lane" for high-priority traffic (and control packets) and another for normal, "bulk rate," packets which can afford to be delayed or discarded and re-sent later. The chip uses VLAN ID tags to identify critical data and place it in the priority queue where it's mixed with low priority traffic on a "space available" basis using a modified deficit round-robin (MDRR) algorithm. If the low-priority queue starts to get backed up, Ample uses a per-port WRED scheme to preemptively drop lower-priority queues before the chip saturates (see Fig. 2). This assures that there will always be enough bandwidth is still available in the link to support the bits in the high-priority queue.

When used for VoIP traffic it ensures that voice quality remains stable even under high traffic loads. According to Ample the MAC can support up to 40% of its capacity as high priority traffic before the algorithm starts to break down. Of course that's what network processors are used for today in many DSLAMs, but pushing much of the bandwidth management out to the MAC allows those expensive chips to be spread across more connections. And that allows a manufacturer to offer equipment that costs less while making the best possible use of a carrier's available bandwidth.

Since hardware speaks louder than any PowerPoint presentation, Ample will be featuring an interesting demonstration at this year's N+I that illustrates just how much processing power can be saved by doing priority queuing at the MAC level. By connecting the Harrier MAC an Intel 2800 NP (rated for 2.5 Gbit/s) and a Cavium security processor, they'll be able to support 12 Gbit/s worth of traffic.

Other chip makers are also exploring congestion management at the MAC level, including Vitesse. But their chip only has 1 queue per port in their chip with no classification. And congestion is managed by a simple "tail drop" technique. Intel is reported to have a chip in stealth mode that has 2 priority queues, but its 2-stage oversubscription scheme divides the available bandwidth among groups three groups of eight ports in a fixed manner instead of managing it on a per-port basis. I'd tend to agree with Ample's assessment that, in some circumstances, Intel's architecture can allow low-priority traffic from one group to block voice streams in another.

For not terribly much more than you'd pay for a "dumb" MAC, Ample can supply you with the intelligence to make better use of your bandwidth, and save you BOM costs elsewhere in your system at the same time. In applications where a standalone MAC is used, it looks like the Harrier is an excellent choice. While many smaller applications, such as workgroup switches, use ASICs with built-in MACs and will not be able to take advantage of Ample's technology, products with higher line densities such as DSLAMs, access switches, and other network edge equipment should provide many sockets for these versatile chips.

The Harrier 12, 24, and 24LS are in production priced at $160 for the Harrier 12 and $195 for the Harrier 24, both in 10-k piece lots.

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