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networkZONE Products for the week of March 21, 2005
Applied Micro Circuits Corporation Says…
AMCC's Dual CDRs Tackle OC-48 and 10G XFP Module Market
With High-Speed CMOS Design and Electronic Dispersion Compensation Expertise
Applied Micro Circuits Corporation (AMCC) has announced the S19233,
a 10Gbit/s dual Clock Data Recovery (CDR) device with Electronic Dispersion
Compensation (EDC) and the S4850, a dual OC-48 CDR. The first in a series
of 10Gbit/s dual CDRs with EDC, AMCC's S19233 is designed for use primarily
in XFP MSA modules. The dual CDR mitigates fiber properties, such as Chromatic
Dispersion and FR-4 traces up to 30", and boasts industry-leading jitter
tolerance (0.8UI) and jitter generation (35mUI) specifications. The combination
of these capabilities enables greater design flexibility and creates a cost-efficient
opportunity for customers to leverage their existing systems for a variety
of applications.
The S19233 supports 10 GbE/FC/SONET/SDH/FEC transmission standards at market-leading data rates from 9.9 to 11.3Gbps. Featuring a small footprint of 6x6 mm², the device contains dual CDRs that provide fully integrated clock recovery signal conditioning capabilities for low-power, 10Gbit/s applications. The S19233 is an integral part of a flexible system solution and can be connected to AMCC's S19237 ser/des device.
"We think the performance of the S19233 as a dual CDR will allow for a greater adoption of the XFP MSA module in the marketplace," said Neal Neslusan, director of marketing for AMCC's transport products. "The newest member of AMCC's proven, CDR/ EDC portfolio demonstrates our commitment to the 10Gbit/s market and expertise in delivering greater functionality in the low-power, high-speed devices our customers require today."
The S19233 can be used in the optical interface of SONET/SDH/FEC/10GbE/10GFC equipment, which consists primarily of the serial transmit interface and the serial receive interface. The S19233's system circuitry consists of a high-speed phase detector, clock dividers and equalization circuitry. The device utilizes on-chip clock recovery/clock clean-up PLL components that allow for the use of a slower external clock reference, 155.52 MHz (or equivalent FEC/10GbE/10Gbit/s FC rates), in support of existing system clocking schemes.
Similar to the S19233, the S4580 CDR derives high-speed timing signals
for SONET/SDH-based equipment but for OC-48 plus FEC data rates. The S4850
receives an OC-48 scrambled NRZ signal and recovers the clock from the data.
The device outputs a differential bit clock and retimed data. Packaged in
a 121-PBGA, the S4850 offers designers a small package outline with low
power dissipation (200 mW/channel).
analogZONE Says . . .
It's over two weeks since OFC and I'm still awash in a sea of product announcements that spewed from that event. One of the more notable items is a pair of dual CDRs from AMCC. The appearance of their S4850 OC-48 part should help drive down the cost of networks that support standard 2.5 Gbit/s and extended (FEC overhead) rates. I'll focus my remarks on their S19233 part because its good mix of features and performance should help accelerate the maturation of the emerging 10-Gbit Ethernet 10GE, FibreChannel, and OC-192 SONET systems. They've employed an all-CMOS design with a bunch of good features that provide more manufacturability and improved performance in lower-cost XFP modules.
From the high level of integration and compact packaging, it's obvious that AMCC put lots of effort into minimizing their footprint within XFP modules. One less obvious but significant feature is their dual CDR. Conventional single-CDR solutions require multiplexing the clock recovery element, something that's fine in practice, but involves adding another chip to your design. It's also very handy for supporting the loopback mode that's required in the XFP standard. And even if you want to use two chips to keep your Tx and Rx paths physically separate, the second CDR can be powered down most of the time and engaged only when loopback is required.
AMCC has also added EDC compensation on their receive path combining non-linear and feedback-based equalization techniques. While AMCC was about as tight-lipped about the details of its EDC circuit as Broadcom was about its EDC chip that I reviewed recently, but, from what I can infer, their digitally-controlled analog feedback element is more effective at cleaning up ISI than a straight equalizer. The spec sheet also seems to indicate that while the on-chip EDC can extend a 10G link up to 100 km its primary mission is improving performance to meet tight SONET specs, even under marginal conditions. But AMCC assures me that devices with longer reach are in the works. Depending on your application the receive EQ can be run in either an automatic or manual adjustment mode.
While the S19233 is primarily aimed at the XFP module market, I'd expect it to find other applications as well. For example, the device's low power, respectable equalization capabilities and good jitter characteristics, could make it a good candidate as a CDR element in 10-Gbit/s serial backplanes.
The S19233 is sampling to key partners in a PBGA-49 with production scheduled for Q3 or Q4 of 2005. The S4850 is also sampling with production later in March 2005. The S19233PBI will be priced at $65 and the S4850PBI at $57, both in 1-k piece lots.
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