networkZONE Products for the week of March 15, 2004
EZchip Says…
Swiss Army NP -- Ezchip's NP-2 Network Processors
Integrate All Major Line-Card Functions
EZchip Technologies (a subsidiary of LanOptics Ltd.) is disclosing
details of its NP-2 family of network processors. The first two models of
the NP-2 family consist of NP-2s, a 10-Gigabit Ethernet/SONET/SDH device
and NP-2e, a 10-Gigabit Ethernet-only device. Both NP-2 devices integrate
a 10-Gigabit duplex NPU (network processor), classification engines, two
traffic managers, ten 1-Gigabit MACs and one 10-Gigabit MAC in a single
chip. The NP-2s also features two SPI4.2 interfaces with up to 192 channels.
Both devices provide the lowest system cost and power for high-density Metro Ethernet and Ethernet over SONET/SDH applications. Sampling for both NP-2 devices is slated for the fourth quarter of 2004, using TSMC 0.13 micron process. The NP-2s is priced at $795 and the NP-2e at $595 in quantities. NP-2 is based on the proven architecture of the now in production NP-1c, uses the same simple programming model and is software compatible to the NP-1c. A previously announced model of the NP-2, integrating TCP offload and Security engines to address the services market, is expected to sample next year. Additional NP-2 models targeting both lower and higher speeds than 10-Gigabit as well as other market segments will be announced separately.
"The NP-2 builds on the success of the NP-1c while reducing system chip count, cost, and power," noted Linley Gwennap, principal analyst of The Linley Group. "The NP-2 is the first announced chip to combine a network processor and traffic manager for full-duplex 10Gbps applications. It enables a lower system cost and far lower system power than any 10Gbps NPU available today."
"EZchip continues its thrust forward to lead the network processors market," said Eli Fruchter, President and CEO of EZchip. "NP-2 solidifies our 10-Gigabit NPU leadership established with the NP-1c by furthering the integration and reducing the system chip count, power and cost. The NP-2s and NP-2e are first in a family of highly integrated network processors that will address more market segments and more speeds. By integrating all of the key line card components into a single chip, the NP-2 addresses a wide range of networking applications in the Wide Area Network (WAN), Metro Area Network (MAN) and data center. Specifically in the cost-sensitive Metro segment, the NP-2 can win over other network processors with its unmatched integration and over non-programmable network ASICs with the unlimited flexibility it provides."
The NP-2 is a highly integrated network processor family featuring 10-Gigabit full-duplex processing in a single-chip. The NP-2 integrates several functions that would normally be found in separate chips: 7-Layer 10-Gigabit duplex processing, classification search engines, two traffic managers for ingress and egress traffic management, ten 1-Gigabit and one 10-Gigabit Ethernet MACs and two duplex SPI4.2 interfaces. The NP-2 uses commodity DRAM for all its lookup tables, frame memory and traffic management control to minimize system cost and power dissipation. For maximum flexibility a choice of DRAM technologies are supported: SDRAM DDR-II, FCRAM-II and RLDRAM-II.
Integrated classification search engines eliminate the need for expensive and power-hungry CAMs or even SRAMs. All types of look-up and classification tables are stored in low-cost low-power DRAM and provide large headroom for application scaling. Two traffic managers provide advanced Quality of Service by supporting DiffServ and IntServ services and a wide variety of mechanisms including: per-flow metering, policing and shaping, WRED congestion avoidance, as well as priority or WFQ hierarchical scheduling. For accurate bandwidth control, a separate traffic manager is provided for both the ingress and egress traffic flows enabling traffic shaping and scheduling after processing has been completed, and prior to transmission to the network ports or switch fabric. Each of the traffic managers with its associated memory chips can be bypassed in applications that use external traffic managers.
The on-chip MACs provide direct connection to ten Gigabit and one 10-Gigabit
Ethernet ports eliminating the need for external MACs. The two SPI4.2 interfaces
can bypass the integrated MACs and provide flexibility to connect to switch
fabrics and Ethernet or SONET/SDH framers. Up to 192 channels are available
supporting virtual concatenation and hitless bandwidth allocation through
the Link Capacity Adjustment Scheme (LCAS).
analogZONE Says . . .
EZchip has come a long way since I first gave them a skeptical review when they announced plans for their one-chip NP. Much of my skepticism has faded with the arrival of working silicon, and even an external traffic classifier. Their lower part count and use of specialized processors that reduce silicon and programming requirements have allowed them to significantly out-perform (at least in terms of throughput) a pair of Intel's IXP 2800 chips by a factor of up to 5x in a typical scenario that performs routing on mixed IPv6 and IPv4 traffic with a route table of about 1 million entries. Reality Check: when pressed, EZchip does admit there is less of a difference in throughput when both chips are asked to do simpler tasks.
And now that they have 33 paying customers (i.e. companies that have bought tools and are actively designing with the parts) and four designs are already in production with its current line of network processors, I'm convinced that they offer a strong value proposition for many applications. Of course, the ramp-up rate for these products is still uncertain, and with only $1.75 million in sales last year ($550 k in Q4) they are still bleeding red ink. This means EZchip will have to move a heap more processors to achieve profitability. The problem is that there is some question as to where the market for network processors is going, especially if they are targeted at the limited amount of high-end equipment that goes into access aggregation and other carrier-oriented equipment.
EZchip has a very ambitious plan to get around this bottleneck by driving down the solution cost of many mid-tier applications. While the per-chip price of their processors is still rather steep, the strategy behind the company's latest product offerings seems to be to absorb as many functions as possible into their device to dramatically cut component count and overall BOM costs.
Their
new NP-2 series builds on the aggressive integration strategy of the NP-1
that put everything from search engines to specialized packet crunchers
on a single chip. The NP-2 is software-compatible with the NP-1 but adds
2 traffic managers that can be configured to handle ingress and egress tasks
(See the block diagram). This is an improvement over the external manager previously
offered which was an ingress-only device that worked mostly with virtual
output queue assignment functions.
With the caveat that EZchip would not walk me through the intimate details of their manager, I'll report that they claim to be able to support wire-speed traffic of 10 Gbit/s (25 Mpackets/s) at any frame size, down to 40 bytes and beyond the 9 kbyte jumbo (they say up to 16 kbyte). You also get statistic collection functions that make billing and accounting much easier.
The engines are supposed to be capable of supporting up to 64 kbyte per flow queues each with 5-level hierarchical scheduling. This means that they can inspect and group traffic into 5 separate queuing schemes that can then be managed according to 5 different sets of scheduling algorithms.
At each level, you can impose a combination of algorithms:
Of course not all applications need bi-directional traffic management, while still others may need additional features or more flows than the 64 kbyte supported by the chip. That's why EZchip allows either manager to be bypassed as needed. As a bonus, turning off a traffic manager allows you to save the cost of the associated memory chips and reduce operating power.
Depending
on the version you select (NP-2s or NP-2e), you get a different mix of Gigabit
Ethernet MACs and SPI 4.2 interfaces tailored for use in either mixed SONET/SDH/Ethernet
environments, or straight Ethernet/IP applications. The NP-2s (s is for
SONET) handles PoS or straight IP over Ethernet with support for the VCAT
and LCAS protocols that allow for much higher granularity (192 STS-1 channels)
and transport efficiency in EoS environments. The processors' integrated
SPI 4.2 works directly with Ethernet aggregators from Vitesse, PMC, and
a couple of other vendors. The fabric-side interface is very flexible and
can be configured to support CSIX over LVDS or SPI 4.2.
The SPI-2e (Ethernet) version sports a 10G Ethernet MAC on its fabric-side interface that can connect directly to switch fabrics that handle straight Ethernet -- i.e. Broadcom's StrataSwitch family & TeraChip's TCF16X10.
Both NP-2s have a host interface that adds a pair of 1GE RMII MACs to complement the PCI interface used by the NP-1. The additional connections give you lots of flexibility in hooking up to the host system and allows you to run look-aside functions like security or offload processing without burdening the PCI bus.
Anticipated power is around 15 W. While this is not insignificant, EZChip says that it's about half of what the Intel 2800 draws (30+W) when it supports half-duplex operation at 10G, and without on-chip classification. Since it uses the same NPU as the NP-1, the existing development tools will allow you to begin writing applications right away, although you will have to wait a while for the extensions that support the traffic manager and other unique architecture additions. EZchip says that since the chip is almost fully-defined, work on updating the tools has already started and the new version should appear well ahead of sample silicon.
While the price of these chips is pretty steep, it's a fraction of the cost of the individual devices they replace. This is part of EZchip's strategy to use a radically lower solution cost to push NPs into everything that shovels large volumes of packets or SONET frames around. This should help drive down the cost of packet processing even further by absorbing most of the remaining functions required to implement everything from an intelligent, QoS-aware 10 Gbit/s server blade to the front tend for an aggregation switch.
EZchip anticipates sampling both the NP-2s and NP-2e in Q4 2004, with production in early 2005. While I'd expect to see at least some schedule slippage (2 - 3 months) on an ambitious project like this, most of my concerns about these chips eventually making it to market are calmed by the fact that much of the NP-2's guts are legacy IP and actually running in the NP-1 series. This, and the knowledge that the initial design is complete with verification and coding already in progress, contributes to a very reasonable vapor index rating.
The NP-2s is priced at $795 and NP-2e at $595 in large volumes. Other NP-2 models will be announced separately.
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