networkZONE Products for the week of March 7, 2005
Freescale Semiconductor Says…
The QUICC Turn Pro: Freescale's PowerQUICC Architecture
Evolves With Faster, Packet-Friendly Communications Engine, Higher Capacity
MPC8360E PowerQUICC II Pro processor family targets converged
packet network market with next-generation QUICC Engine technology designed
for multi-protocol interworking and Layer 3 packet processing
The evolution to packet-based networks is reshaping wireline and wireless access, requiring communications equipment makers to deliver Internet Protocol (IP) convergence solutions that are cost-effective and compatible with existing software. Freescale Semiconductor is addressing this convergence/compatibility/cost challenge with next-generation PowerQUICC processors based on a PowerPC core and a new, packet-friendly communications engine.
Freescale's MPC8360E PowerQUICC II Pro processor family with QUICC Engine technology provides an advanced yet backward-compatible communications processing solution designed to drive down the cost of developing packet-based networking and wireless equipment. Based on the e300 PowerPC system-on-chip (SoC) platform, the family consists of the MPC8360E and the MPC8358E processors, both of which contain Freescale's innovative QUICC Engine technology. (E designates on-chip encryption; versions without integrated security engines are also available.)
"Freescale's QUICC Engine technology is the most significant development in the PowerQUICC family since the creation of the PowerQUICC architecture a decade ago," said Linley Gwennap, principal analyst of The Linley Group. "QUICC Engine technology turbocharges PowerQUICC performance on data-plane tasks such as interworking, switching and parsing. Even with this more powerful engine, Freescale is offering the new enhanced processors at a very competitive price."
The MPC8360E family with QUICC Engine technology is designed to provide optimal price/performance and a balance of powerful control plane and data-path capabilities for the cost-sensitive "sweet spot" of the IP convergence market. Target applications include IP DSLAMs, voice over IP (VoIP) systems, 3G wireless infrastructure, passive optical networking (PON) equipment, multi-service access platforms and enterprise routers.
"Bringing QUICC Engine technology to the PowerQUICC II architecture makes perfect sense for cost-sensitive, mainstream packetized applications," said David Perkins, senior vice president of Freescale and general manager of Freescale's Networking and Computing Systems Group. "Since QUICC Engine technology is scalable, we can easily extend it into more powerful Freescale processors to serve more demanding packet-based applications."
QUICC Engine technology is an evolutionary leap forward for Freescale's RISC-based Communications Processor Module (CPM) -- a key element of PowerQUICC architecture. Freescale's new communications engine delivers the packet throughput, interworking capabilities (without CPU intervention), multi-protocol support, high channel density and software compatibility that equipment manufacturers need to develop advanced yet economical solutions for converged packet networks.
Based on Freescale's SoC methodology and designed for scalability, the MPC8360E family's QUICC Engine technology features two RISC processors, each running at up to 500MHz. This architecture enables QUICC Engine technology to deliver a combined full-duplex data throughput of up to 1.2Gbps including interworking. Eight Unified Communication Controllers (UCCs) provide support for Gigabit Ethernet, HDLC, and UTOPIA / Packet over Sonet (POS) at up to OC-12 speeds.
QUICC Engine technology offers exceptional channel density for cost-sensitive, packet-based applications. For high-density VoIP systems such as media gateways and IP PBXs, QUICC Engine technology supports more than 2,000 voice channels, about three times as many as Freescale's Communications Processor Module. It also enables development of IP DSLAMs that support up to 256 subscribers, achieving high density levels to help reduce system cost.
The CodeWarrior QUICC Engine utility, a graphical user interface (GUI) tool from Freescale, is available to accelerate and simplify initialization and configuration of drivers and communications protocols managed by QUICC Engine technology. The tool provides an easy-to-use, menu-driven environment that enables developers to handle common QUICC Engine initialization tasks. Key features include protocol conflict notification, as well as immediate access to documentation via "mouse-over" functionality and drop-down menus.
Along with QUICC Engine technology, the MPC8360E family's features and enhancements make it ideal for today's and tomorrow's wired and wireless access equipment and enterprise networking equipment. It offers:
The MPC8360E family is software-compatible with previous PowerQUICC communication
processor generations. The family is supported by CodeWarrior development
tools from Freescale and by a comprehensive ecosystem of development tools,
operating systems and applications from third-party vendors working through
Freescale's Smart Networks Alliance Program. This backward-compatibility
and extensive ecosystem support helps to preserve software investments,
minimize development overhead and speed time to market.
analogZONE Says . . .
The second-generation PowerQUICC II family has enjoyed immense popularity in the telecom world, thanks to power and application-specific features it provides. Over the years, they've added more processing power, enhanced I/O capabilities, and embedded security functions (see our review), but much like the Great White Shark, the inherently robust design has remained essentially unchanged over the equivalent of a millennium in Silicon Valley Years. This has changed with the latest incarnation of the QUICC II line which greatly enhances its functionality while maintaining code compatibility and solid linkage to its earlier QUICC brethren.
Besides
adding raw throughput and a faster PowerPC processor (see Fig. 1), the
changes are meant to expand the processor's TCP/IP and packet-handling capabilities
to help meet the demands of newer convergence-oriented (everything-over-IP)
applications. To this end, the biggest change in this spin is the New "QUICC
Engine" which replaces the venerable "communication processor
module" (CPM) that performs most of the low-level traffic handling
without bothering the embedded PowerPC core.
The new QUICC Engine more than doubles the CPM's
processing power with 2 RISC engine cores (future versions will have up
to four) that use an enhanced version of the CPM's proprietary architecture
(see Fig. 2).
Unlike the MIPS or ARM cores you find in many packet processors, they are
purpose-built from the ground up to handle packet inspection, table lookup,
and manipulation Some of the enhancements enable single-clock execution
of many common operations. Other tweaks to the instruction set allow the
engine to work closely with other on-chip accelerator cores that support
buffer pool management for lookup, table searches, etc for support of complex,
multi-layered protocols. Of course, the wider 64-bit internal data bus (up
from 32 bits) allows everything to "breathe" easier. 
The new QUICC engine is much more flexible, has more throughput and does more communication processing (3x to 4x) without intervention from the PowerPC. Its greatly strengthened internetworking capabilities keep inspection lookup, and other L3 functions in the RISC engine rather than having to push them through the main PPC CPU (see the "eye chart" in Fig. 3 for full list of stuff handled by new QUICC engine). Most of the old multi-channel communications controllers (MCCs) have been replaced by eight "unified communications controllers" which handle both fast and slow communications channels, and are designed specifically to terminate TCP-based links. The UCCs can be programmed to serve as MAC functions for nearly any protocol or data format from UARTs to Gigabit Ethernet or high-speed TDM.
There is still a holdover MCC but it's been enhanced to support an integrated multi-channel TDM with up to 256 logical channels. It supports up to eight T1/E1 lines or a pair of T3/E3s for easy interfaces to telco-based WAN connections.
As I mentioned the new family of PowerQUICC II Pros is software-compatible with the earlier generation, but adds lots more compute power thanks to an enhanced e300 PPC core and a clever DDR memory controller. The controller allows the 64-bit DDR interface to run as a single 64-bit channel, or can be split into a pair of 32-bit channels, one of which can be used to give the QUICC engine its own memory rather than sharing it with the PowerPC core. Another subtle but important "tweak" is the asynchronous clocking between PPC and RISC engines that allows the PPC and the QUICC engines to run at different speeds. The addition of independent PLLs for each CPU and other logic eliminates some of the timing dependencies that made some applications difficult in earlier chips.
It's interesting to note that the 8360 does not offer native RapidIO, a feature that's still only on the PoweQUICC III platform. While it's not confirmed that subsequent high-performance versions of the chip will sport RapidIO interfaces, Feescale has already announced that the new QUICC Engine will migrate up to QUICC III family - and probably in its 4-CPU form. And Since Freescale has converted most or all of its critical IP to transportable cores, we can also probably expect Seaport packet processing elements to end up embedded in the QUICC III as well.
Freescale
has also broken with its long-standing policy of keeping the code that ran
its communication processors very tightly controlled and not accessible
to (most) customers. In the past, they only permitted some limited configuration
and use of strictly-controlled 3rd party microcode. But this has changed
as they've now opened up the code for the new RISC engines and their associated
cores to customer programming. Their new QUICC Engine is being rolled out
with a full suite of development tools and utilities that will enable customers
to "roll their own." One of the big things that makes it possible
for "civilians" to program this deeply into the chip is the enhanced
Code Warrior package from Metrowerks package that enables unified development
of both PPC and RISC engine code with coordinated timing and resource management.
The 8360E enjoys the same large library of pre-developed applications and
APIs as its predecessors, but also features a greatly-enhanced collection
of TCP/Ethernet-oriented Internetworking applications and device drivers
(see Fig. 3).
With such a complex chip to program, developers will also appreciate the new configuration tool that enables GUI-based set up and management of the QUICC Engine and its associated UCCs. It also automatically links defined channels to the appropriate drivers in the API to save development effort. This clever chunk of software will also save many hours of frustration by linking the development tasks being performed to the specific parts of the 5000-page manual. For example, when a resource conflict or other problem arises it directs developers through the massive electronic manual, opening the appropriate page for the task at hand.
The QUICC II Pro actually comes in two flavors -- the 8360, which is full-featured, and the 8358, which is pin-compatible but offers more limited performance at a lower price. Saving $10 cuts out two of the eight UCCs, eliminates the remaining MCC, changes the memory interface to a single 32-bit DDR, and gives you as single Utopia interface. Power for the 8360 is typically in the 3-5W range, depending on speed and port loading, with a little less for the 8358.
The 8360/58's re-engineered communication engine and the native multi-protocol capabilities it provides should enable low-cost solutions for lots of emerging IP-oriented applications. Its combination of the packet processing and internetworking found in a conventional network processor, plus its powerful control plane processing capabilities has the potential to BOM costs dramatically. This plus its versatile interface capabilities should win it homes performing DSL aggregation to Gigabit Ethernet in IP-DSLAMs, running SME routers, powering multi-service access nodes, and aggregating services in wireless Infrastructures, IP-PBXs, and many more boxes where converged media is now the norm.
Limited samples for Q3 2005 and 10-k piece pricing will be under $45 for the 8360 and under $35 for the 8358.
|
| ||||
