networkZONE Products for the week of February 16, 2004
Parama Networks Says…
Amazingly Dense Microchip -- Parama Networks Introduces
The World's First "ADM-on-a-Chip"
High Integration, Flexible Architecture Reduces Equipment
and Network Costs While Providing a Seamless Migration to Next Generation
SONET-Based Mesh Networks
Parama Networks has introduced a complete system level solution for
the design of next generation SONET/SDH transport equipment. The solution
includes Parama's groundbreaking ADM-on-a-Chip, a companion SONET/SDH Overhead
Processor, a Data Transport Processor, a Hardware Reference Design, and
an Advanced Software Development Kit.
The core of this solution is the ADM-on-a-Chip, an innovative "system on a chip" (SoC) that features the highest level of integration to date and an elegant architecture that simplifies the equipment design process. The ADM-on-a-Chip offers -- for the first time on a single piece of silicon -- all of the functions necessary to build an ADM and other next generation network equipment, including cross-connect, line and tributary framers, and overhead processing.
As a result, the ADM-on-a-Chip allows network equipment vendors to upgrade existing systems and build entirely new systems that cost one-third the price of and consume one-fifth the power of currently available systems. Due to the high level of integrated functionality, an ADM-on-a-Chip-based complete system level solution can be developed in one-fifth the time, again compared to currently available products, thus allowing quick time to market and improved return on investment. As such, the ADM-on-a-Chip will offer a powerful economic incentive to service providers to reinvest in their networks, as part of the evolution of SONET and SDH networks into the "convergence" transport networks needed to efficiently transport data and traditional voice traffic.
"Service providers are looking for ways to cost-effectively and quickly leverage their SONET networks to deliver next generation managed data services. Parama's ADM-on-a-Chip aggressively addresses this problem, with benefits expected for both legacy and emerging next generation network elements," said Dean Casey, former Director of Optical Transport Network Architecture for Verizon.
"Given the improving economic indicators in telecommunications, in general, and the market discontinuity between legacy and next-generation ADM systems, in particular, we are launching our product at an opportune moment" said Hemant Bheda, CEO of Parama Networks. "Furthermore, our product addresses the most critical concern of our customers, as the cost of ADMs and similar network devices are now dominated by electronics, not optics. With worldwide sales of ADMs alone reaching $3 billion in 2003, we have a huge market opportunity and we are well-positioned to fully participate in the coming wave of capital spending."
Traditional merchant silicon providers typically design "building block" ASICs that can be combined by systems vendors into elements, line cards, and subsystems. These silicon providers lack the overall system knowledge required to define a complete SoC solution that would meet service provider's requirements.
The Parama team, however, has been able to achieve this feat of engineering
as a result of their unique blend of systems level and chip design experience,
including a SoC methodology with "first pass silicon to production"
success. Advances in silicon VLSI technology over the last few years, combined
with a patent-pending compact cross connect implementation, now enable entire
ADM implementations on a single piece of silicon, which create dramatic
reductions in cost and power while providing scalability, flexibility, density
and simplicity in building the next generation of data aware SONET and SDH
systems.
analogZONE Says . . .
Parama's new line of one-chip ADMs is one of the rare happy byproducts of the telecom boom/bust cycle. Originally intended to be a proprietary ASIC buried deep within a carrier-class box, the chip would probably never have been commercially available until the company found itself stuck in the huge crater left by the 2001 implosion of the communications industry. Unlike most companies, this scrappy little firm actually had some working alpha silicon to fall back on, and a few prototypes of their chassis to use for development. Rather than call it quits, they decided to roll the dice (pardon the pun) one last time and re-work their designs into commercially-viable general-purpose chips.
It looks like their gamble may have paid off. They
now have working samples and made a semi-stealth roll out in early January.
I was taken by surprise and could not pry loose enough time to cover the
announcement when it came across my desk. But the product was so intriguing
that I made it a point to track down Parama and visit their Santa Clara
labs when I was out at DesignCon last week. The trip was quite
rewarding as I got to take an in-depth peek at their chip, and the industrial-strength
development chassis they cobbled together out of one of their the prototype
boxes. Getting to actually watch a line card-sized ADM in action was lots
of fun, and very impressive.
Shrinking of a box-sized piece of equipment to a single card is possible because both their PNI8040 40-Gbit/s and PNI8160 160-Gbit/s devices handle all the high-order framing, add-drop, overhead processing, and cross-connect functions that usually require five to a dozen high-power ASICs to accomplish. Depending on which chip you're looking at, the line-side interface consists of a pair of OC-192 or OC-768 interfaces and high-order framers. This allows you to get on and off a honking-big fat pipe, while the non-blocking cross-connect that sits between them allows you to divert time slots to any one of eight programmable-rate framers with STS-1 granularity. These smaller tributary framers can be programmed to dole out bandwidth at all standard rates down to the OC-3 level.
About the only functions that are handled externally are
the overhead processor that runs in parallel with the chip, and the transport
processor which sits between the processor and the tributary optics. They
are currently implemented in FPGAs, but will eventually become dedicated
silicon -- if volume and consensus on needed features permit. Using FPGAs
is a very sensible move for a start-up with limited resources, and the extra
cost of an FPGA will not be noticeable in the first round or two of products.
A programmable solution also allows a high degree of flexibility to support
whatever protocol(s) or special features you wish to use.
The current reference design for the FPGA-based data transport processor supports transparent GFP, a critical element in providing efficient EoS services, and generally making better use of the bandwidth in SONET-based networks. From what I was able to see at the lab, I'm fairly confident that Parama will live up to its promises to introduce a second-generation data transport processor that will support frame-based GFP. The current version also supports the virtual concatenation (VCAT) protocol that will enable even better use of SONET for delivering packet-based services, including metro Ethernet. Plans are in the works to support the emerging LCAS link aggregation protocol that will enable rapid re-provisioning of user connections to add or subtract bandwidth as needed.
The FPGA-based overhead processor is a complex beast that handles all standard SONET/SDH section and line overhead processing tasks. It also provides connectivity to all the necessary interface buses in the ADM-on-a-Chip. It combines a PCI bus for host bus interface, an ADM-on-a-Chip control bus interface (2 ports), an overhead bus interface (2 ports) for interfacing to two ADM-on-a-Chip devices and a private communication channel (PCC) bus interface. It also has a DRAM interface to enable support for DRAM based buffers for supporting HDLC or PPP over the PCC.
The net result is that these chips allow you to put the of the ADM function in a third the space it now requires while cutting the cost by the same factor and using 1/5 of the power. Besides making it possible for the ADM to now simply be a part of another box, the chips allow the cost of electronics to track the steadily-declining price of optical interfaces, something that could dramatically change how and where ADMs are used. In fact, the savings are significant enough that it could change the economics of access equipment dramatically, and allow deployment of SONET much closer to, and often right at the subscriber location.
If Parama delivers on its promises, its products
will permit ADM functionality to be distributed across a network in novel
ways, such as embedding it within DWDM equipment or access muxes. When you
see a single card replacing a rack-full of equipment it's easy to contemplate
all sorts of possibilities.
But wait, there's more.
The Parama ADM supports the virtual/logical ring structure required to implement SONET-based mesh network architectures. These mesh networks are much more flexible, enable much deeper deployment, and better use of bandwidth than traditional ring structures. Much like packet-based mesh networks, meshed SONET systems can be deployed incrementally, allowing providers cost-effective options for establishing or expanding their networks. There is an excellent paper on SONET mesh architectures that was co-written by Parama and Telcordia Labs that you can download from Parama's web site.
Until now the big downside to meshed SONET was the fact that they did not recover from equipment failure, "backhoe fade," or other disruptions in the same quick, predictable manner that ring architectures do. While acceptable in the IP/Ethernet realms, the non-deterministic recovery characteristics of mesh SONET kept it from being considered for use by telco-grade carriers.
Parama has solved this dilemma by including hardware hooks and support software that enable deterministic link restoration that mimics ring behavior during the restore operation. Space, and the limitations of my understanding, won't permit a full discussion of the technology, but from what I can see, the Parama's deterministic self-healing mesh may well change the market dynamics of both SONET equipment and the services they deliver.
The combination of lower cost and more flexible topologies is potentially disruptive for the relatively staid SONET infrastructure market. If Parama can penetrate the market and overcome its natural conservatism, they will give birth to equipment that allows operators to make better use of existing fiber and to change topologies of existing networks easily.
Of course having the right development tools will also be important for market acceptance. While I'm not a software expert, Parama seems to have done a good job at building on the tools it had for in-house development work to produce high-level software that allows you to write code in terms of the application, not the architectural oddities of the chip. The well-provisioned development tool set, plus the ability to mess with the FPGS-based transport and overhead processors allows for quick customization of a reference design, or a build-up from "scratch."
The parts are sampling in 0.13-micron CMOS in a BGA-1521. The PNI8040 is priced at $1250 in 1000-piece lots, and the PNI8160 at $2500.
My concerns about an extremely ambitious first-time product are considerably offset by the existence of working hardware to earn Parama a very respectable Vapor Index Rating.
Data Sheet
PNI8160
Data Sheet
PNI8040
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