networkZONE Products for the week of February 9, 2004
Xignal Technologies Says…
Solid To The Core -- Xignal's 10 Gbit/s CMOS Transceiver
Core IP Offers High-Performance, Ultra-Low Jitter
New 10-Gbit/s CMOS Transceiver Improves Data Transmission
Performance in Local, Metro and Wide-Area Networks
Xignal Technologies AG has released its new 10 Gigabit per second (Gbit/s)
CMOS transceiver design. The product, which exhibits a transmitted clock
jitter of less than 200 fsrms (femto seconds) and no measurable
crosstalk between receive and transmit path, sets a new world record in
jitter performance for high-speed CMOS designs. All achieved jitter values
(jitter tolerance, jitter generation) far exceed SONET/SDH requirements
to significantly improve data transport equipment performance and reach.
Xignal's XT38702 10 Gbit/s transceiver is designed for applications such as OC-192/STM-64, 10 Gbit/s Ethernet or 10 Gigabit Fibre Channel. It is also suitable for 10 Gbit/s copper connections in backplane, shelf-to-shelf and rack-to-rack applications.
The XT38702 is a completely integrated transceiver consisting of a limiting amplifier, clock and data recovery (CDR), demultiplexer, clock multiplying unit (CMU) and multiplexer. No additional external components are needed to operate the device, which features a power consumption of less than 1W. Due to the integrated limiting amplifier, the input sensitivity of the 10 Gbit/s SerDes (Serializer/Deserializer) is less than 15 mV.
"With the XT38702, Xignal continues to deliver highly sophisticated analog designs to the market," said Holger Hoeltke, Vice President of Marketing at Xignal. "With its unprecedented performance and its CMOS implementation the device may readily be integrated in a System-on-Chip environment or be used as a stand-alone IC for data transport applications."
The XT38702 10 Gbit/s transceiver is suitable for data rates from 9.95
Gbit/s to 10.7 Gbit/s. Several functions, including the power-down modes,
have the ability to be programmed via a serial bus interface. The XT38702
10 Gbit/s transceiver uses 0.13-µm standard CMOS process which guarantees
high performance at a very low power consumption level.
analogZONE Says . . .
In the four years since its founding, Xignal has rightly anticipated a growing need for doing the tough analog design work required to fabricate high-performance PLL, DAC, ADC, and other analog elements in standard CMOS processes used in the major foundries. It appears they have now successfully applied their expertise to produce the XT38702, a 10-Gbit/s serial transceiver, whose performance can make your life easier in other areas of your design. I expect that the core will find a place in many merchant ICs and custom ASICs because 10-Gbit/s serial interfaces in Ethernet, Sonet, and FibreChannel are becoming increasingly common, while the expertise to design them is not.
The XT38702 takes four 2.5-Gbit/s SerDes signals, and multiplexes them into a single 10-Gbit/s interface. It's designed to run a laser driver (like those found in small form factor modules) directly, and boasts its own integrated limiting amplifier. If you want to drive copper (such as an XFI 10GBIC copper module), you can easily do so by adding a low-cost discrete driver.
Xignal boasts some extraordinary jitter-specs that far exceed the stringent SONET/SDH requirements for 10-Gbit/s. For example, the core has demonstrated a jitter generation level of less than 200 fsrms, over 3x better that the SONET/SDH requires. It also has a measured phase noise at under -118 dBc at 1 MHz offset. Xignal says achieving these numbers is in large part thanks to a very careful PLL and VCO design but won't elaborate on details. While Xignal was less than forthcoming, I was able to learn that part of their performance comes from the use of proprietary substrate isolation techniques that limit crosstalk and other parasitic effects. The tight jitter specs they deliver should allow you more margin in the rest of your design, or to improve the jitter budgets in your system, allowing for longer link lengths.
I do have some concerns about whether it will meet these aggressive specs when "in-country" in real-world deigns, because Xignal was a bit vague about how they produced their test data. For example, I'm not sure how much packaging parasitics and noise from adjacent devices may add their own degradation to the core's performance, but from what I can see of their design it is an excellent place to start from. The substrate isolation should greatly assist in keeping the VCOs from responding to noise, but it will also take some good layout and management of metal runs -- especially in applications with multiple 10Gbit/s interfaces.
The core is currently designed to run on TSMC's 0.13 micron process, but Xignal says it can be adapted to UMC or most other foundry processes which support their required feature set. Xignal's expertise somewhat offsets sketchy information, and concerns over implementation issues, earning it a reasonable vapor index rating.
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