networkZONE Products for the week of February 3, 2003
TeraChip Says . . .
Lots Of Crunch, Low Sodium - TeraChip's 16-Port, Low-Power,
160-Gbit/s Generic Switch Fabric Works With Most Traffic Managers And NPs
TeraChip has introduced the TCF family of single-chip cell-switching fabrics. First in a series of fully scalable solutions, the TCF16X10 is the industry's only operational 160G single-chip switch fabric.
The TCF16X10 offers network system vendors the highest available bandwidth density on a single chip, and drives fabric solutions that are scalable to 1.28 terabits. Based on the Company's patented memory-based technology, the TCF16X10 is a fully integrated, cost-effective switch fabric that requires no scheduler, thereby reducing system complexity. Its simple implementation means faster time-to-market and improved product margins for switch vendors serving the local (LAN), storage (SAN) and metro (MAN) markets.
"The combination of scalability and simple system design makes the TCF an attractive off-the-shelf option for switch vendors," said Jag Bolaria, senior analyst at The Linley Group. "By helping vendors reduce system development time and complexity, TeraChip has taken a major step in positioning itself as a leading silicon player in this fast-growing market."
A result of breakthrough technology featuring 64 SERDES, 0.13-micron design, the TCF16X10 is a low-power 15W chip with extensive quality of service (QoS) and redundancy capabilities. The TCF16X10 enables outstanding flexibility in system configuration, with the same fabric supporting line cards ranging from 10-40Gbps.
"Within just two years, our experienced team of designers has successfully
delivered one-chip switch fabrics to the market," said Micha Zeiger,
TeraChip founder and CEO. "Our solutions address the market need for
single-chip fabrics that simplify system design. Based on extremely positive
market feedback, we are confident that the TCF16X10 will help switch vendors
reduce development costs and shorten time to market."
analogZONE Says . . .
Although you probably won't mistake this switch fabric for the snack chip by the same name, one can only hope this new product is as tasty as its namesake. Tasty or not the fact that these folks are going straight after Marvell and Broadcom's switch fabric offerings is a pretty bold move. It's even bolder when you consider the tough times they are launching into, where even most established network semiconductor houses are scratching for business. They must be doing something right though, to have gotten the large chunk of VC money to put this project together in the middle of a down market.
I think that a good part of what TeraChip's is doing right is that they have spotted a real market opportunity for merchant switch fabric. While the major switch/router companies will probably rely on some of their own silicon to implement their "secret sauce" in, switch fabrics are mature enough that a merchant chip set will often make more sense than an ASIC.
Of course, Broadcom and Marvell also offer highly-competitive switching solutions (heck, I gave one of them an analogZONE product of the year award) But while they are both excellent products, their fabric is closely tied to their traffic manager, permitting relatively little deviation from the reference design they supply, or opportunity for product differentiation.
TeraChip on the other hand, has designed the TCF16X10, the first in a product line of high-density, scalable (to a point) switch chips that sport a generic interface (CSIX/SPI-4.2 with NPSI modifications for flow control.) Rather than be tied to a particular architecture, the generic interface allows you to easily hook up whatever merchant, or custom, silicon you wish in the network processor and traffic manager sockets. All the traffic manager need do is create a CSXI-standard header that contains the destination port address, as well as information about packet length, priority, and other vital information.
Each 16-port fabric chip has 160 Gbit/s total capacity, which can be aggregated to make fabrics with up to 1.8 Tbit/s of bandwidth. As with any shared-memory fabric of this type scaling is an issue, but the current size at which this starts to become an issue is of little consequence for most applications.
With their first engineering samples in hand, they claim that power is 15 W/chip, or a tad less than 1 W per port. For comparison, Marvell's Prestera chip set consumes roughly 18 W per 12 ports, but don't take this too seriously since I am not sure if this includes the controller element or just the switch fabric.
Looking a bit more closely at the TCF16X10, we see the 16-port switch uses a shared-memory cell-based architecture, a feature common to some of the more successful merchant switch fabrics on the market today. But besides its generic interface the TeraChip also distinguishes itself by packing its shared RAM on-chip. In addition to the obvious cost savings, I expect you also get wicked-low latency since the normal chip-to-chip delays associated with external RAM are eliminated.
Of course there is only so much memory you can cram on a chip, even at 0.13 micron line widths. And with 128 queues (16 ports, 8 queues per port), there is just not enough room for all the cells required to have a memory location for each and every possible queue position. To get around this, the TeraChip architects have developed a very clever dynamic queue allocation scheme that lets them efficiently use a significantly smaller pool of on-chip memory to support virtual queue depths that are greater than the chip's physical capacity. While I normally get nervous about this sort of design stunt, the details I learned under NDA give me at least a reasonably warm feeling that the available memory will not saturate under any reasonable (and most unreasonable) traffic conditions.
Digging deeper into the switch's guts, we see that all control signals that govern stuff like Multicast, and QoS are handled in-band as special control cells that are read by the ingress and egress controllers. Because control messages are so easily replicated, the chip can cheerfully perform single-clock multicast. Another oddity of the TeraChip is that its cell length varies between 40 and 165 bytes, adjustable in increments of 20 bytes. I'm not quite sure how they can support deterministic cell-based behavior with such a scheme but, for the moment, I guess I'll take their word that it does.
The fabric supports a scheduling function based on a weighted round robin (WRR) state machine. All weights are user-programmable (via the serial host interface), and allow streams to enjoy various levels of priority without starving low-priority queues. The scheduler also allows some, or all traffic to be scheduled according to strict QoS priority rules. This allows the fabric to provide support of TDM and other high-priority time-bounded traffic.
As I mentioned earlier, the switch fabric supports the SPI 4.2 and CSIX interface standards via its on-chip SerDes circuits. Each set of four 3.125 Gbit/s serial lanes can transfer 10 Gbit, with enough room for signaling overhead. In its normal "standards-based" mode, the chip employs scrambling for dc balance on top of the traditional 8B/10B coding that usually provides both dc balance and some basic error detection.
If signal integrity in your design permits you can turn off the 8B/10B coding and leave error detection/correction to the internal mechanism on the fabric, or to higher levels. Dropping the coding overhead increases throughput significantly, and Tera says that scrambling is just as effective for dc balance. While this jibes with the little I understand of line coding theory, I'm not enough of an expert to fully agree or disagree with them on this point. Hey, if anyone out there is actually reading this, I'd welcome any reader's opinions or insights.
Regardless of TeraChip's claims about the value of scrambling, you can always fall back and program the chip to provide the conventional line coding. The cool thing here is that you can use this switch fabric in 8B/10B mode to retrofit existing systems, or work with switch controllers that require it.
So what you have here is a very flexible switch fabric chip with low power and low cost-per port. It can be also support redundancy for high-availability carrier-class systems. Thanks to its open architecture you can use it to retrofit with existing platforms, or even aggregate lanes for future upgrades.
My latest conversation with them confirms that their alpha silicon is back from the fab. and seems to be working on the first spin. Tera also says that their evaluation boards are up and running at this point. With a cost of around $50 per 10-Gbit port, TeraChip has a chance to win a good chunk of this tight market - if it can overcome the stigma of being an orphan (stand-alone part), and the potential support problems this implies.
Part of this problem can be taken care of by providing adequate tools, and the manufacturer seems to have addressed this quite satisfactorily. TeraChip says they have put together both a reference platform (480 Gig chassis) including line cards and a full suite of software development tools, including drivers, APIs, and a bit-accurate, event-driven simulator. If the tools are as good as they claim, they should make it relatively easy for designers to "build" a system and know its performance before they actually assemble it.
The other half of gaining market acceptance is to show you really do "play well with others" by getting included in a few reference designs. The folks at TeraChip told me that they are already partnering with at least one major NP/Manager silicon vendor on reference design, and in preliminary discussions with a few others. If successful, this will help crack the market and encourage 3rd-party software companies to support their products.
Availability of working alpha silicon, plus an ambitious but credible architecture earns these tasty switch chips a low sodium rating.
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