networkZONE Products for the week of January 20, 2003
EZChip Technologies Says . . .
Management Made EZ - EZchip's QX-1 10-Gbit/s Traffic
Manager Cuts Cost And Space, Supports 1K VoQs, 28K Egress Queues
EZchip Technologies is pleased to offer the immediate delivery of its QX-1 10-Gigabit traffic manager. QX-1 further enhances the considerable savings and flexibility brought about by EZchip's leading NP-1 10-Gigabit network processor. The combination of the highly integrated QX-1 and NP-1 enables building networking equipment with the stringent requirements for Quality of Service (QoS) while significantly reducing overall system cost, power dissipation and chip-count. EZchip is employing a unique model by offering QX-1 to its customers the choice as a readily available ASIC (Application Specific Integrated Circuit) or as a core for applying QX-1 in FPGA (Field Programmable Gate Array), providing flexible cost structures and enabling customer-specific features and interfaces.
"In the past year EZchip has accomplished significant milestones: We have brought to market the NP-1, a solution two generations ahead of the competition, we have garnered a substantial customer base and successfully raised $24.5M Series C funding, establishing EZchip as the leading high-speed network processor vendor. Our recent Series C funding also provides us with the long-term viability customers expect when engaging with a new supplier." said Eli Fruchter, President and CEO of EZchip. "The availability of QX-1 is the first in a series of milestones we aim to achieve in 2003 to further solidify our market leadership through continuously enlarging our customer base and broadening our product offering."
EZchip's QX-1 is an optional device that expands the traffic management capabilities of the NP-1 10-Gigabit network processor for applications requiring advanced QoS provisioning. Unlike other solutions that have been announced that implement traffic management through software programming of the network processor, EZchip's QX-1 implements traffic management in hardware for high performance. Since traffic management involves simultaneously examining the status of thousands of queues and their related parameters it can be effectively implemented only in hardware. Software implementation dictates successive inspecting of thousands of individual queues resulting in poor performance, complex programming and inaccurate provisioning of QoS.
QX-1 is used to deliver QoS in 10-Gigabit interfaces, multi 1-Gigabit Ethernet line-cards with twelve or more ports, as well as OC-192, 4 x OC-48 and 16 x OC-12 Packet over SONET (POS) applications. QX-1 is a single-chip traffic manager providing advanced queuing, scalable frame memory, congestion management and hierarchical scheduling of network traffic consisting of thousands and millions of flows.
EZchip's QX-1 delivers significant advantages to customers designing switches and routers for the metro, carrier edge and core:
analogZONE Says . . .
I've had a rather long and occasionally turbulent relationship with EZchip, and its CEO, Eli Fruchter. Their early announcment of the ambitious NP-1 10-Gbit/s network processor caused some serious skeptisicism on my part, but as my review last year shows, they have delivered both the original processor and an enhanced version. But despite a string of 14 design wins, reality has settled in and even EZChip has acknowleged that in many applications a network processor is not enough, with some of the heavy lifting being done by other dedicated hardware. Enter the QX-1 traffic manager chip.
Some applications, like high demand on line cards that connect to many ports and support large numbers of streams will inherently create enough traffic management issues to swamp a programmable processor unless it gets some hardware assist. The QX-1 should handle these situations well, by providing shaping, scheduling, and congestion management using hard-wired logic that can execute complex policy-based queuing decisions on many streams without any assistance from the NP. You can select, and adjust, the parameters of several commonly used management algortihms including WRED, WFQ, WRR, strict priority (overrides WRR), and guaranteed or rate-limited bandwith. The manager has an internal hierarchal scheme with three levels of queuing, allowing you to support three distinct tiers of service. Each level can be programmed seperately with its own policy and rate-service management algorithms to provide real service differentiation.
The QX-1 is designed to take advantage of its companion processor's (the NP-1 or NP-1c) unique CAM-less classification capabilities.The NP-1's on-chip classifier generates and pre-pends a classification header onto each packet before it passes it on to the QX-1. This header contains the queuing information required for the manager to place it in one of the appropriate input or queue memory locations. It even has sufficent information to identify the packet's source URL - a feature which, as we'll see later, comes in handy for certain types of load balancing. When used for ingress queuing, the DRAM-based buffer can support up to 1000 VoQs, up to 128K output or egress queues.
Like the NP-1, the QX-1 has a cleverly designed memory interface that allows the use of inexpensive external DRAM for buffers rather than faster, but more expensive (and power-hungry) SRAMs. It also has a scalable memory architecture that lets you use anywhere between 4 and 12 chips depending on the depth of the queue the application requires.
The QX-1 swings both ways, and is equally happy managing traffic as it emerges from a network processor, or as it leaves a switch fabric on its way to the NP. When used in egress mode you can hook it directly to the NP-1's SPI-4.2 interface. The manager also has a CSIX interface which is useful for interfacing to a variety of merchant switch fabrics or for performing ingress mode management. In ingress mode, the QX-1 masquerades as a switch fabric by using a second on-chip CSIX interface to hook up between the NP-1 and the fabric. This mode prevents switch fabric congestion (HOL blocking) and resulting dropped packets.
I've always liked the fact that EZchip's software tools make its somewhat complex processor architecture transparent to programmers without sacrificing performance. In the past year things have got even better as EZchip's development software library has seen lots of new additions, including reference code for layer 2 switching IPv 4& 6 routing, MPLS, URL-based load balancing (Web-switching), and NAT, with others to come. They are also working with the communication software company LVL7 to develop APIs to support most major protocols.
Fruchter claims that the new tools and library code stacks are now regularly allowing customers to crank out the software portion of a new NP-1-based design in three months using a small programming team of only two or three people. I'm somewhat skeptical that a complex development effort could be this easy, but he insists that there have been several design efforts in several of the 14 companies using Ezchip devices that have delivered results this quickly with only two or three developers. Given how Ezchip has made good on its earlier claims, I guess I should take his word for it - at least for the moment.
Another nice thing about the QX-1 is that it's also available as FPGA code that can be licensed for insertion into a single Xlinx series 4000 chip. There are enough gates to spare that customers can add different interfaces (CSIX variants or customer proprietary) and other specialized functions to fit their needs. While most folks will probably use the actual chip in clean-sheet designs, I know that the FPGA version will come in handy to customers who have existing designs that need to be freshened up rather than scrapped - something that's increasingly common today in a time of tight development budgets.
The same (relatively) low gate count that allows the QX-1 to squeeze into a single FPGA also begs the question about whether it can be further integrated with other IP on a single chip. I think it may be a big stretch to see a one-chip NPU/classifier/traffic manager in the near future, but given EZchip's penchant for successfully executing daring designs, I would not put it past them. Watch this space...
EZchip's QX-1 is sampling. Pricing will be $695
in 10-k piece lots with separate one time fees.
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