connectivityZONE Products for the week of October 17, 2005
SiliconPipe Says…
SiliconPipe's Stair Step Package Unclogs 10G Backplanes
& Interconnects With Less Power, Less Silicon
New approach to high-speed interconnectivity eliminates package
vias, lowers solution cost
SiliconPipe, an Open Source Intellectual Property Company, has announced
its new high-performance StairStep BGA IC packages. The new Stair Step package
design offers designers a quick and easily implemented solution to high-speed
signal integrity. The use of the package can be accomplished using today's
manufacturing techniques, with little or no modification.
The new Stair Step package is a high-performance, low-cost substrate solution that use tiered of "StairStepped" contacts at the package edges. This design sequentially exposes the interconnection layers of redistributed circuit connections with no vias or stubs. It adds many advantages beyond today's traditional PGA packages. The package addresses the I/O density problem along with cost, providing significant performance and reliability improvements, while reducing the manufacturing cost.
"Most engineers involved in high-speed digital design understand that the connections, or transition regions, in a circuit cause many difficulties. Thin, coplanar structures are good for high-speed systems, because thin structures minimize the size and bulk of these transition regions, improving transmission line impedance control and also crosstalk. At high speeds, thin, structures look good to me, and this is such a structure," says Dr. Howard Johnson, the author of High-Speed Digital Design: A Handbook of Black Magic, the 'Signal Integrity' columnist for EDN magazine and a frequent guest lecturer at Oxford University."
Cost Savings
The cost savings are significant due to the reduction in the number of manufacturing
steps and especially the elimination of plated vias. The improved, simpler
structural elements of the package, allow for improved manufacturing yields.
There are fewer steps, with no drilling, or plating required. This is a
100% savings in the costs associated with via processing. The electrical
testing cost should also be reduced, if not eliminated. Since the package
uses individual layers, each layer can be inventoried and used to create
custom packages, including mixed-pitch I/O if desired, on a moments notice.
The design costs are also reduced significantly. Signal layers are directly
converted to micro-strip or stripling through added metallization, resulting
in little of no signal integrity tools or experts needed. There is less
material used in the design, which equates to a 30% savings in material
cost.
Performance Improvements
The performance is enhanced by the elimination of the plated vias, which
add cost, consume routing space, and introduce signal performance issues,
such as: crosstalk. Impedance control, and reliability. Using the StairStep
package, differential pairs, common in high-speed circuit design, can be
designed for virtually zero skew and crosstalk can be almost completely
eliminated. The package offers designers a very clear channel, allowing
for lower voltages for signal transmission. The designer has the opportunity
to design internal I/O terminations. Via related impedance and cross-talk
are eliminated. This means zero impedance change, and zero via crosstalk.
Reliability Improvements
Reliability is the key to success with this package. One obvious improvement
comes from the elimination of the plated vias. This means 0ppm in via defect
rate.
"The Achilles Heel of high-speed design, platted vias, have been eliminated with our new Stair Step package," comments Kevin Grundy, President and CEO of SiliconPipe . "Having a clean channel means better signal integrity, using lower voltages results in less power requirements."
Ease in Adoptability and Manufacturing
The use of the new StairStep package enables designers to move forward in
overall system performance improvements. They can use the StairStep methodology
beyond the IC substrate, and continue to improve performance along the entire
signal path. Since the new package uses current materials and manufacturing
techniques, such as flex or rigid material, optical inspection for electrical
performance is possible with now new test probes. The package uses an all-lithographic
process with no serial drilling needed. The ability to make continuous,
reel-to-reel, makes it ideal for flow manufacturing techniques.
analogZONE Says . . .
So what's a rabid silicon maven like me doing reviewing SiliconPipe's packaging technology? The simple answer is that while connectivityZONE has been traditionally mostly involved with the chips that glue complex systems together, it's becoming increasingly apparent that as system speeds increase, connectors, cables, substrates, packages and connectors become an increasingly integral part of the electrical design. While Silicon Pipe is far from the first company to realize that there is an increasingly complex interplay between silicon and these so-called "passive" components as data rates increase, they've taken a novel holistic approach to high-speed interconnects that has the potential to cut power and overall system cost for backplane and other interconnects at 10 Gbit/s and up.
My experiences with analogZONE's "Great Gigabit Backplane Challenge" lead me to agree with SiliconPipe's assertion that good channel design allows much less complex, power-hungry chips to deliver good reach and margin at high (5 - 10 Gbit/s) data rates. Until now, however, the added cost of exotic PCB materials, back drilling and other added process steps have usually made it cheaper to simply pony up for more equalization, echo cancellation, and whatever other signal processing could be crammed into a SerDes transceiver.
This is because the problem of boosting transmission speeds in PCBs and backplanes has usually been dealt with in a piecemeal manner by chip, connector and board manufacturers, each determined to fix all the deficiencies on their side of the fence. SiliconPipe has crossed these traditional boundaries and developed a packaging system that takes a different approach to balancing the equation that defines the relationship between silicon costs, backplane costs, and overall system performance.
Much like the whole-system thinking that is behind
it, SiliconPipe's technology is much more than the Stair Step package described
in the release. But we'll start there before going over the design methodology
that the packaging enables. At its simplest, the "Stairstep" packaging
provides direct, impedance-controlled connections to all critical signal
paths that deliver them directly to the PCB traces, without vias.
Using their custom-developed "Off-The Top"
trace layout methodologies, designers can create direct connections between
the Stair Step IC packages and direct-to-connector traces on the board for
all the high-speed signal paths. While it works best when it's used on a
PCB that has counter-sunk cut-aways that expose each layer of PCB traces
directly, Stair Step packages can be used on normal "flat" board
surfaces with solder balls to fill the gap between the package's pad and
the board's surface. 
Breaking out the chip's most critical signal paths and directing them to the PCB layer(s) of their choice allows designers to selectively add high-dielectric materials to one or two layers of the board, or to even continue using "vanilla" FR-4 in some cases. Physically partitioning the high-speed portions of the overall design also allows you to concentrate your efforts and resources on the toughest problems and use conventional layout and materials on the 50% - 80% of the remaining lower-speed and power/groundplane traces.
SiliconPipe also claims you can realize significant cost savings because their system lets you use extremely simple microstrip and stripline design techniques that provide very well-defined performance without rigorous analysis. According to the company it allows experienced designers to visually inspect a design and know it will work instead of running it through a time-consuming analysis cycle.
While I'm not an expert on PCB/Backplane manufacturing it looks like the small incremental costs required to adapt this unique packaging concept to a design should be more than offset by the use of simpler, less costly (and power hungry) transceivers and, most likely, fewer PCB layers. This is borne out with some early tests that SiliconPipe ran with Aeluros' Puma 10G XAUI transceiver chip (reviewed April 2003). Their small-scale lash-up allowed the chip to deliver roughly 3x its normal reach using 1/8th the voltage swing (100 mV vs 800 mV) it usually required.
These promising results indicate that SiliconPipe's packaging and design technology should be a good fit for many "first meter" applications where optical interconnects are too expensive and bulky. The novel IC package coupled with new approaches to connector and PCB design eliminates vias for high-speed signal paths. Depending on the reach and speed of the connections you're designing it should extend the utility of conventional FR4 and fabrication techniques or minimize expensive the use of exotic PCB materials.
All this seems very promising, or I would not have taken the time to write it up, but I'd like to also offer a couple of notes of caution here. First, the test setup described above was a proof-of-concept demonstration and, despite the excellent results, I'll hold off final judgment on its commercial viability until I see a full-up system running with a couple of dozen active SerDes lanes. The other issue is that there are currently no commercially-available connectors to support the SiliconPipe interconnect scheme. The proof-of-concept test used standard connectors whose pins had been modified, something early adopters might have to do for their first systems. Hopefully we'll see Tyco or some other major interconnect house step up to support SiliconPipe with some prototype connectors for full-scale system testing and to help bootstrap the early market.
After hearing their story I think that all the technical issues are solvable and that SiliconPipe's biggest challenge will be getting market traction within the relatively conservative mechanical design and manufacturing culture that is slower to adopt changes than most other parts of the electronics community. Fortunately, the technology can be adopted incrementally. For example, the StairStep package can be used with standard non-countersunk boards with good results, something that might be able to help SiliconPipe get some early market acceptance.
The other thing SiliconPipe has going for it is an open source marketing strategy that will give the technology away to manufacturers (but require a low-cost certification process) and generate revenues from licensing their IP to manufacturers and OEMs. To make it more attractive, they'll offer licenses on a straight per-product per-year basis (much like many CAD companies) with no per-unit royalties. Since selling standalone IP is one of the tougher businesses to be in, I'm not sure if this is their long-term strategy or just a placeholder to generate some revenue until they're bought out by a CAD company, or an electronics hardware manufacturer. But, in either case, the potential savings in design effort, manufacturing costs, component costs and lower power could be attractive enough to change the way interconnects are done at 10 Gbit/s and above.
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