i/oZONE Products for the week of September 30, 2002
Cypress Semiconductor says . . .
Thanks4 The Memories - Cypress Semi's QuadPort
Memory Family For Datapath Switching Wireless Basestation, Storage Subsystem
and WAN Switch Applications
Cypress Semiconductor Corporation is pleased to offer its next-generation high-performance QuadPort Datapath Switching Element (DSE), which supports bandwidths up to 27 Gigabits per second (Gbps) and provides a density of 5 Mbits. Cypress's QuadPort DSE is a four-port switching element that allows simultaneous access to an integrated memory array from each of its completely independent ports operating in different frequency domains. The device can help eliminate contention and arbitration issues on a shared bus when multiple processors or functional blocks need access to the same data, thereby significantly improving overall system performance.
Cypress pioneered the concept of QuadPort DSEs with the introduction of its one Mbit family (10 Gbps bandwidth) in 2001, including functions such as 2 x 2 switching, datapath aggregation, redundant data generation and packet header manipulation. This next-generation QuadPort DSE family features higher bandwidth (4 ports x 167 MHz x 40 bits) and simultaneous access to the data array from all four ports. The new QuadPort DSEs are offered in 128 Kb x 40, 64 Kb x 40, 32 Kb x 40 and other configurations.
"These high-performance devices put Cypress a generation ahead of the competition and allow our customers to create innovative system architectures, thereby achieving higher performance and efficiency," said Geoff Charubin, marketing director for Cypress's Data Communications Division. "By providing up to 5 Mbits of integrated memory at 27 Gbps operation, the QuadPort DSE enables our customers to reduce the need for multiple devices, thereby significantly lowering their cost-per-megabit of capacity and cost-per-gigabit of bandwidth."
QuadPort DSE Innovates System Architecture
The QuadPort DSE, when considered early in the design cycle, shows its strength
as a communications datapath enabler because its combination of logic and
memory creates a non-blocking switch architecture. For example, the devices
may be used as:
When used in conjunction with the Cypress OC-48 port SERDES, Delta39K CPLDs and HOTLink family of backplane physical-layer devices, the QuadPort DSE family provides a complete system solution for customers building communications linecards. Communications systems customers who are already familiar with Cypress's Quad Data Rate RAM, BEAST FIFO, synchronous SRAM, CPLD, and clock solutions will also benefit from these QuadPort Switch devices.
QuadPort DSE Features
This QuadPort DSE family of devices offers configurable I/Os supporting
LVTT Land SSTL2 standards, enabling seamless interface with PLDs, FPGAs,
ASICs, next-generation DSPs, control processors and other memory devices
on the board. These devices also come with advanced features such as impedance
matching on data outputs to reduce transmission line effects; burst counters
for enabling block transfer of data; and memory block retransmit for rereading
a block of memory without loading the initial address.
All QuadPort DSEs offer four completely independent ports that can simultaneously
access the data storage array and operate in different frequency domains.
Each port can read or write data up to 167 MHz, giving the device up to
27 Gbps of data throughput or bandwidth. Offered in a 676-ball PBGA package
measuring 27 mm x 27 mm with a 1.0 mm pitch, these devices are compliant
with IEEE 11149.1 JTAG boundary scan for a high degree of manufacturability.
analogZONE Says . . .
Cypress Semi's introduction of its family of quad-port RAMs is one of the more intriguing additions to its extensive family of specialty memories that I've seen in years. Cypress applies the fancy term "Datapath Switching Element" (DSE) to these souped-up memories, but I think they are justified applying the label because of the fundamental changes in networking system architecture they should make possible. In addition to simple storage, buffering, and broadcast, the shared-memory concept is great for separating clock domains within a system. Their support for simultaneous reads from all ports (at up to 167 MHz) makes an excellent way to tie together multi-processor arrays and all kinds of other system elements.
In RAID-based SAN systems, you could use one or more of these DSEs for fast, efficient datapath switching. Since you can cascade these versatile critters, you can add as many ports as needed to support multiple paths or to provide redundancy management.
The Cypress DSEs' ability to efficiently link multiple DSPs should make it a natural for use in radio network controllers and baseband cards. With an efficient way to tie multiple DSPs together, it will be easier than ever to create parallel processing architectures that can easily be scaled to the task at hand.
They should also find a warm welcome in WAN linecard designs where Cypress says that their they can be used to aggregate and de-skew multiple feeds. I have a feeling that you will also able to use these parts' ability to single-handedly share and manipulate data to create very cost-effective data path packet manipulation or network search engine designs.
You can get these chips with bus widths of 18, 20 and 40-bits, and up
to 5 Mbits in size. If you need something larger, it's easy to cascade the
DSEs in width (no problem!)or depth (providing you can afford the latency)
as needed.
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Cypress says to expect the first chip (2.5 Mbits deep, 40-bit wide) samples
late 4Q. Cost is pegged at $115 each in 10K quantities.
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