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connectivityZONE Products for the week of September 26, 2005
Synopsys, Inc. Says…
Synopsys Offers Low Power PHY IP For PCI Express,
XAUI and SATA
Mixed-Signal IP complements Synopsys' market-leading portfolio
of serial interface controllers
Synopsys, Inc. has expanded its DesignWare Mixed-Signal intellectual
property (MSIP) portfolio with new ultra low-power PCI Express, XAUI and
SATA physical layers (PHYs) in the 130- and 90-nanometer (nm) processes.
These high-performance, mixed-signal PHYs offer highly differentiated, advanced
built-in diagnostics for evaluating link performance and margin. When combined
with the DesignWare digital controller cores and verification IP for PCIe
and SATA protocols, the new PHY IP provides an optimized, lower risk, single
vendor solution for designers incorporating these protocols in their system-on-chips
(SoCs).
The new PHYs provide numerous benefits to the SoC designer, including compliance to the relevant standards specifications, the industry's smallest cores, low jitter and high receive sensitivity, resulting in a lower system bit error rate (BER) and a robust design with maximum margin and minimum power. The new solutions allow designers to significantly reduce power, requiring only 30 to 50 percent of the power consumption per lane of present solutions. These PHYs are based on an advanced analog architecture designed to scale to the next generation of data rates and process technologies as new high-speed SERDES protocols evolve.
Today design engineers developing SoCs for networking, storage, computing and consumer applications use PCIe, SATA and XAUI PHY's for high-speed interconnects operating at speeds from 1.25 gigabits per second (Gbits/s) to 3.125 Gbits/s. Testing links at these speeds, however, Synopsys' new PHYs incorporate advanced, built-in diagnostics - accessible through JTAG (Joint Test Action Group) - that are designed to replace traditional external loopback pass-fail testing with testing the link margin at speed. This approach is far superior because it allows designers to measure the eye-opening directly and verify the integrity of the signal, channel, and receiver while using only a conventional low-speed digital tester. This advanced approach reduces the total cost of ownership of the PHYs by providing excellent test coverage of the analog nature of high speed PHY's without using sophisticated high-cost test equipment. Support for Automated Test Equipment (ATE) is provided by delivering simple pass-fail JTAG vectors that ensure maximum test coverage when the PHYs are tested in production without the need for developing a complex test program.
"With the addition of the new PCIe, SATA and XAUI PHYs to its IP portfolio, Synopsys clearly demonstrates its commitment to delivering low-power, high-performance interconnects," said Jag Bolaria Senior Analyst at The Linley Group. "These new PHYs are very low in power consumption and include advanced features such on-board diagnostics and ATE."
"The release of the new PHYs firmly establishes our leadership in
Mixed-Signal IP and in complete solutions for PCIe, SATA and XAUI. We are
now targeting the next generation of high-speed, high-performance serial
interconnects," said Guri Stark, vice president of Marketing, Synopsys'
Solutions Group.
analogZONE Says . . .
Synopsys' addition of a versatile set of PHYs for PCIe, XAUI, and SATA, transceivers to their already-sizeable IP collection supports its strategy is to embrace an ever-larger chunk of the value chain by offering most, or all of the commonly-used cores and IP used in their customer's designs. Given the abundant use of these interfaces in most modern designs, I'll expect that these PHY cores will help attract and retain customers to Synopsys' platform, as well as generate considerable IP licensing revenues. While not reviewed here, it's probably also of interest to note the release of what they claim to be the Industry's first spec-compliant PHY for the new Wireless USB spec.
It's apparent that Synopsys has used their considerable analog design talents to make these three serial PHYs extremely compatible with the rest of their design elements and the fab processes that they run on. One example of this is how all three PHYs share lots of common elements and requirements. Despite somewhat different speeds, drive current and timing requirements, all the cores share a common transceiver design (CDR, PLLs, front end and driver circuitry), that's differentiated using digital logic which forms sort of a "digital gasket" that configures the analog elements. For example, the spread-spectrum capabilities used in SATA and PCIe are generated by configuring the TX and RX PLLs' loop control logic. While I'd have to know a little more about these cores' digitally-controlled analog interfaces than Synopsys wanted to share with me before I was completely comfortable with the concept, I'll agree with them that it allows the cores to be directly embedded in, and play well with the rest of a Synopsis-based design.
Synopsys says that their PHYs have been designed for low power -- an important feature in XAUI applications like switch fabrics which can have a hundred or more lines. Sadly, Synopsys was coy about providing me with detailed information about the inner workings of their PHYs, something that made it a bit hard to verify their performance claims. I was able however, to learn that their XAUI interface provides some basic programmable transmit pre-emphasis and simple "boosting" to handle the attenuation that occurs in longer runs. These features are not currently available in PCIe and SATA, but when I pointed out that it might help improve reach and avoid problems in marginal situations I was told to "watch this space." I had another "watch this space" moment when I pointed out that SAS and SATA PHYs are very similar electrically and asked about support for DAS interfaces. I was told that while their SATA PHY already can already drive a SAS connection, there is no SAS MAC element in Synopsis library just yet.
As I said earlier, Synopsys' reluctance to discuss details of their transceivers with me makes it hard to have full confidence in their claims for low power, or the conditions under which they measured a power consumption of less than 200 mW for a 4-lane PCIe PHY (including the clock module) - a figure that's 30% - 50% lower than most equivalent drivers. The advertised power rating for their XAUI PHYs is a bit higher(spec of 226 mW for four lanes ) due to the faster 3.125 Gbit/s rate but Synopsys' is still quite low compared to what Broadcom, Marvell, or most other manufacturers offer today. For the moment I'll accept that their power numbers are at least "in the ballpark" and see if I can find any real-world data that supports or challenges this assumption.
One of the reasons I'm inclined to accept Synopsys' power claims is that I suspect much of their designs derived from Accelerant, a high-speed SerDes transceiver manufacturer acquired by the company a couple of years back. I got to know these chips quite well during my research for the reviews that appeared here between 2001 and 20003 and saw all the features they touted actually working. Most notably these PHYs share Accelerant's unique and very useful abilities to sample and analyze their own signals for bit error rate (BER), jitter, and margin with almost no external test equipment. They do this using a unique "BERT-on-chip" function and the ability to extract eye diagrams via the JTAG interface that enable you to determine the signal's jitter (both deterministic and random) level. I can speak knowledgably, and favorably about this part of Synopsys' cores since Accelerant freely shared (under NDA) information with me about the theories and technologies behind them.
The ability to accurately analyze a XAUI, SATA or PCI channel with little or no test equipment can a handy thing to have in development efforts. In production it simplifies traditional loop-back testing by using on-chip diagnostic logic to set max and min levels required to test voltage and phase margin on hundreds of links in milliseconds. In service it makes field testing a particular link a quick and painless procedure. Synopsis has built on this by providing a package of test vectors that can be quickly inserted into your test software with little development time.
The DesignWare SATA and XAUI PHYs are available in limited production for 130- and 90-nm process technologies. The DesignWare PHY for PCI Express is available now for volume production. All IP is available in several flavors that allow it to be produced wide variety of TSMC's 130-nm and 90-nm fab processes. Cores are available for the LV, LVOD, and G processes in 130 nm and G, GOD and GT in 90 nm.
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