i/oZONE Products for the week of September 16, 2002
Broadcom says . . .
Server Supercharger - Broadcom's ServerWorks is First
I/O Bridge to Support PCI-X and Gigabit Ethernet
ServerWorks Corporation, a Broadcom company has begun sampling the Champion Ethernet I/O Bridge (CIOB-E), the first core logic to integrate Gigabit Ethernet (GbE) on a chip. The new ServerWorks I/O bridge can be used with all versions of the company's Grand Champion SystemI/O core logic. ServerWorks' SystemI/O core logic technology manages the flow of data to and from a system's processors, memory and peripheral input/output (I/O) devices.
The CIOB-E includes two integrated GbE adapters, each capable of full-duplex operation at speeds up to one Gigabit per second, along with a PCI-X bus controller. The tight integration of these features improves system performance and reduces system cost. The CIOB-E eliminates the need for discrete GbE interfaces, reduces system board real estate requirements, and facilitates the use of GbE in space-constrained server blade applications.
"Gigabit Ethernet on an I/O bridge represents a major milestone for the convergence of computing and communications technology," said Raju Vegesna, President and CEO of ServerWorks. "Integrating high-performance communications technology directly into the core logic reduces costs, increases bandwidth and standardizes Gigabit Ethernet as the primary connection in all servers."
Gigabit Ethernet, the De Facto Standard for Servers
The Ethernet controllers on the CIOB-E contain a full range of features
that optimize system performance and manageability. Each Ethernet Media
Access Control (MAC) unit includes two high-speed MIPS processor cores that
can be utilized for advanced packet filtering and CPU off-loading. The CIOB-E's
MAC uses the same set of drivers as Broadcom's highly successful NetXtreme
family of GbE controllers. In addition to the dual MAC capability, the CIOB-E
integrates two Ethernet physical access layer interfaces (PHY) that operate
with standard twisted pair wiring at speeds of 10, 100 or 1000 Megabits
per second. An alternative version of the CIOB-E, known as the CIOB-ES,
supports differential signaling to an external SERDES interface for optical
and backplane applications.
The CIOB-E is the first ServerWorks product to leverage Broadcom's technology
and market leadership position in the Gigabit Ethernet MAC, Gigabit PHY
and SERDES arena. Other important technological resources that ServerWorks
has garnered through its relationship with Broadcom include TurboTeaming
technology, which provides for a 50% performance gain when two Ethernet
ports are used in conjunction with one another. A dual-Ethernet board configuration
is often used in rack mount servers and blade-based servers. Also, ServerWorks
customers benefit from a host of drivers and manageability software including
Intelligent Platform Management Interface (IPMI) 1.5 and Alert Standard
Forum (ASF), which aid in remote diagnostics and control functions.
analogZONE Says . . .
Hoo ha. While I'm occasionally critical of their missteps, it looks like Broadcom has hit a real home run here. This latest product takes the strengths of both its own formidable collection of PHY-layer IP, and couples it with the I/O know-how of their ServerWorks acquisition in a highly effective manner. To tell the truth, I've been mulling over whether this part is more appropriate in the networkZONE or i/oZONE, and have finally put in the I/O area because I think it marks the beginning of a sea change in the way high-capacity servers are built.
The CIOB-E and CIOB-ES are logical integrations of a 64-133 MHz PCI-X host bridge, and a pair of complete Gigabit NICs (10/100/1000 with auto negotiation.) Besides being an excellent space-saver for high-density 1U/2U server boxes and blades in bladed servers, the integration (plus a move to 0.13 micron fabrication) cut power significantly from 10-20 W in a typical implementation, to 5 W. But wait, there's more.
As everyone knows, the PCI bus is getting long in the tooth and just barely keeping up with the bandwidth demands found in high-capacity servers. The tighter coupling between the Ethernet ports and the host bridge afforded by these chips makes much better use of the PCI bus and avoids many of the bandwidth-robbing bottlenecks found in conventional solutions. In addition, the chips use a proprietary inter-modular bus (IMB) to connect host, south and I/O bridges efficiently at up to 3.2 Gbit/s. While I am not usually a fan of proprietary busses (I'd have preferred to see one of the standards-based SERDES links here), I'll admit this makes some sense in this application. While it keeps you captive to ServerWorks, it does allow you to mix and match of different ServerWorks components while eliminating PCI-X bus contention, arbitration cycles between connections, enjoying significantly lower latency than a generic bridge architecture.
This would be interesting enough, but when coupled with Broadcom's unusual Gigabit MAC, the story gets downright kinky. It turns out that this core is much more than a vanilla network MAC, and packs a pair of custom-built 32-bit RISC CPUs that run the MIPS instruction set. This lets the MAC perform all kinds of packet inspection and filtering tasks as well as limited packet processing and manipulation on its own. While not comparable in power to say a Motorola C-3, one could look at this chip as a lightweight network processor disguised as a bridge chip. What's more, the drivers for the on-chip NICs are the same as the ones used by Broadcom's discrete NIC MAC/PHYs. Besides making it possible to tap into a large base of pre-developed software, you can use Broadcom's suite of development tools to implement any "secret sauce" you wish to add yourself.
Some of the features you can build into the chip include fail-over load balancing (port aggregation) and "smart load balancing". The latter was a port aggregation technique developed by Broadcom that ties ports together at the IP level (instead of the MAC level supported by 802.3). This eliminates the need for the switch side connection to support the procedure, something that only high-end switches do at the moment. It also allows ganging of multiple NIC chips for aggregating in high-traffic applications.
The processor's deep packet filtering capabilities support header parsing to permit a variety of tasks - these include flow classification and port aggregation, plus wake-on special packet, designation of a dedicated management port, and routing of packets of interest to designated destinations and advanced processing. This means that these bridge chips can be the basis of more sophisticated follow-on system-level products, but the folks at ServerWorks are purposefully vague about what these applications are.
Perhaps we can infer something of their future directions from the CIOB-ES,
a complimentary part to the CIOB-E, which supports differential signaling
to an external SERDES interface for optical and backplane applications.
Stay tuned for further developments…
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