connectivityZONE Products for the week of August 14, 2006
Altera Corporation and Sarance Technologies Say…
Altera, Sarance Technologies and Cortina Systems Join
Forces to Deliver First Interlaken Protocol IP Core for FPGAs
Targets high-speed networking and storage equipment, demonstrates
Stratix II GX FPGA capability in 6.375-Gbit/s applications
Altera Corporation has teamed with design services provider Sarance
Technologies and communications semiconductor specialist Cortina Systems
to announce the availability of the industry's first FPGA-based Interlaken
intellectual property core to speed design of network systems applying the
Interlaken protocol.
The Interlaken protocol IP core, created by Sarance Technologies, lets communication and storage network equipment developers apply the new interconnect specification using Altera Stratix II GX FPGAs. Together, the IP and FPGAs enable more cost-effective solutions for 10-, 20-, and 40-Gbit/s interconnect designs in next-generation network switches, routers and storage equipment.
"Our IP is a complete solution that enables customers to rapidly deploy Interlaken-compliant technology in high-performance applications using Altera's Stratix II GX FPGAs," said Farhad Shafai, vice president, R&D at Sarance Technologies. "The IP provides all of the robustness and scalability of Interlaken using a minimum amount of FPGA resources. The core is comparable in size to existing Service Packet Interface Level 4 (SPI-4.2) solutions for 10 Gbit/s applications. By applying this Interlaken-compliant core on programmable logic devices, developers can immediately begin new designs incorporating this protocol specification."
The Interlaken protocol is a royalty-free specification jointly developed by Cortina Systems and Cisco Systems for makers of high-performance network components and equipment. The specification builds upon the logical structure of SPI-4.2 interface technology, now widely used in networking equipment. It preserves the capabilities of SPI-4.2 with multiple logical channels and back-pressure information, while eliminating its bandwidth ceiling and curtailing associated pin-count cost. Interlaken's 90 percent chip-to-chip signal trace improvement increases performance and reduces both board and chip design costs.
"The Interlaken protocol eliminates the cost and performance barriers of existing interconnect standards by taking advantage of high-speed, multi-channel serial interconnect technology to enable the highest density networking equipment," said Zino Chair, vice president of marketing at Cortina Systems. "Altera FPGAs, with their outstanding multi-gigabit transceiver technology, provide an exceptional platform for realizing the potential of the protocol."
Interlaken allows greater integration in network system designs by providing a framework for channelized packet interfaces built upon a flexible and highly efficient serialization/de-serialization (SERDES) physical layer. Using the latest 6.375-Gbit/s SERDES technology enables interface designs that scale from 10 to 100 Gbit/s and beyond.
"This partnership results in IP enabling communications systems
designers to cost-effectively support chip-to-chip communication above 10
Gbit/s," said John Sakamoto, senior business unit director at Altera.
"Our Stratix II GX SERDES supports speeds from 622 Mbps to 6.375 Gbit/s
and provides flexible bonding options that maximize the advantages of the
Interlaken protocol."
analogZONE Says . . .
Sarance's FPGA-based core is the first but, I suspect, not the last commercial implementation of the Interlaken packet-based chip-to-chip SerDes interconnect protocol announced earlier in 2006. Interlaken is in its early stages of adoption but I expect it to do well because it's a non-proprietary standard that fills an emerging need for efficient, low-power, low-overhead multi-Gigabit connections in networking and communications equipment. Implemented on Altera's Stratix IIGX family of FPGAs (reviewed here) the cores can either serve as shims between the new generation of networking silicon with native Interlaken interfaces and legacy silicon, or allow you to create your own Interlaken-capable design in programmable logic. NOTE: If you're not familiar with it, details on the Interlaken Interface specification can be found on the Cortina Systems web site.
This core has its origins in work that Altera, Cortina and Sarance did to provide compliance models (including a bus functional model ) to support interoperability tests for Cortina upcoming products. While they are still rather tight-lipped about actual products, I'd speculate that we'll see an Interlaken-ready version of their Barcelona 24-port aggregating MAC (reviewed here) or their Palermo OC 192/48 integrated framer some time before the end of 2006.
After developing the FPGA core to help Cortina verify its
own silicon, Sarance has unleashed it for commercial use. The IP can be
scaled to different bandwidths by varying clock speed (0 - 6.375 Gbit/s)
and/or the number of SerDes lanes it uses. Thanks to Altera's advanced SerDes
technology, each transceiver dissipates only 240 mW running full-out at
6.375 Gbit/s (see Fig. 1).
The system-side parallel interface is designed to work well with Altera's Atlantic interface bus protocol but can be adapted to other interfaces as needed. Depending on the capacity you're looking for, this parallel bus can either be configured as either 64 (up to 10 Gbit/s), 128 (up to 20 - 24 Gbit/s) or 256 bits (40 - 48 Gbit/s).
Sarance has done a good job on squeezing their IP into a relatively small footprint within an FPGA. For example, a 10 Gbit/s interface requires two SerDes lanes, uses up around 5 kbyte worth of LUTs and 50 kbyte of FPGA-based memory. This compares nicely with the 4-kbyte LUTs and 100 kbyte of memory required to implement a typical for SPI 4.2 interface. And unless you want to go for an eight-lane 40-Gbit/s connection (which requires 25-kbyte LUTs and 150-kbyte memory), you can implement the interface using Altera's less-costly mid-level speed grade parts.
And if you have a few LUTs left in your design, Sarent also has some optional but extremely handy test features that were originally developed for validating Cortina's silicon. These include an integrated PRBS generator that can generate random payloads automatically and the ability to break the Interlaken protocol in a controlled manner. You get the ability to do stuff like fail a lane by inserting CRC errors, alignment errors, or payload errors while monitoring all the receive side's response recovery and alarm modes.
Right now there is precious little (actually, zero) merchant silicon sporting an Interlaken interface besides Altera's FPGAs. But Cortina has assured me that they have several products in the works and that there are "several other networking silicon vendors" doing the same. Unfortunately neither Altera nor Cortina was willing to reveal any of the other companies that are preparing to introduce products with Interlaken interfaces. But the fact that the technology is being provided royalty-free to the industry by Cortina and Cisco tells me that there's a good chance that the standard should be able to gain market traction (see my earlier Editorial "That Big Sucking Sound") for a bit more on why I'm so gung-ho about Interlaken.
Interlaken cores for the Stratix II GX FPGAs are available from Sarance Technologies now for 10-Gbit/s and 24-Gbit/s data rates. A 40-Gbit/s core will be available by the end of Q3 2006. Pricing is based on licensing arrangements with a list price of $17,500 per design for the 10-Gbit/s interface. The 20-/24-Gbit/s interface lists for $25,000 per project and the 40-Gbit/s interface costs $37,500 per project.
Data Sheet Stratix II GX
Data
Sheet Interlaken Interface IP Core. Pb-free is
available.
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