i/oZONE Products for the week of July 28, 2003
Accelerant Says . . .
Thinking INSIDE The Box -- Accelerant's SerDes Transceiver
Provides Upgrades For Existing & New FR4 Backplanes To 10 Gbit/s
Intelligent Silicon Technology Validated in 60+ Systems with
10?18 Bit Error Rate; Adaptive Equalization Unlocks Hidden Bandwidth and
Enables System Upgrades
Accelerant Networks has announced availability of its AN6425 6.25 Gigabit per second (Gbit/s) quad backplane transceiver, the first in a family of low power, high speed SerDes (Serializer-Deserializer) transceiver products.
Targeted for 6.25 Gbit/s data rates with the industry's lowest power consumption of 160mW per full duplex backplane channel, the AN6425 marks the migration of Accelerant's technology to .13u CMOS requiring less then 1W as a quad including I/O ports. Results have clearly demonstrated the ability of the single chip device to deliver from 1 Gbits/s to 10 Gbits/s over existing backplanes, with a typical Bit Error Rate (BER) of better than 10?18. This reliability rating is orders of magnitude greater than the industry's typical BER specification of 10?12. The AN6425 is the industry's most efficient backplane transceiver solution integrating all the elements needed to enable existing system upgrades.
System developers must answer customer demand for increased bandwidth and port density, while reducing overall cost per bit. Today's backplane data rates of 622 Megabits per second (Mbits/s) to 3.125 Gbits/s have traditionally been a bottleneck, limiting the amount of bandwidth that existing systems can support. Accelerant has proven that hidden, useable bandwidth exists in these backplanes through actual transceiver testing on more than 60 systems, enabling developers to meet this demand within currently deployed systems.
"Networking, storage and server system manufacturers all share the same desire to offer end customers enhanced port density and bandwidth to lower overall cost per bit," said Bill Hoppin, vice president of marketing for Accelerant Networks. "With fewer end customers implementing wholesale changes in installed chassis, system developers are looking for cost-effective ways to upgrade their customers' existing equipment. We believe our focus on reliable high speed transmission over existing low cost interconnects, as opposed to depending on expensive new materials and techniques, paves the way for enhanced bandwidth where systems developers need it: in the installed base of equipment."
"Accelerant's 10 Gbit/s SerDes technology works great over our broadband backplanes," said John Webley, CEO of Turin Networks Inc. "Increased backplane link speeds support higher bandwidth blades, which means higher port densities and lower costs for our MSPP and cross connect (DACS) customers. The distributed fabric architecture, used in Turin's Traverse platforms, makes it possible to add blades that use higher speed backplane links without obsoleting deployed blades or requiring upgrades to any common equipment."
Based on Accelerant's intelligent silicon technology, the device uses adaptive equalization to unlock hidden bandwidth in existing, low cost FR4 backplanes common to network, server and storage equipment currently installed worldwide. Adaptive equalization compensates for the loss and inter-symbol interference of older, less optimal backplane interconnects and enables signal transmission up to ten times faster than previously possible. Using Accelerant's technology, very low bit error rates can be maintained with minimal power consumption.
"Rather than developing new systems, OEMs are focusing on extending the life of existing systems," said Jag Bolaria of the Linley Group. "Accelerant offers developers the ability to operate at very high data rates over installed backplane interconnects with high reliability and low power consumption. Consequently, system developers can offer their customers greater bandwidth while staying within power and thermal requirements of the existing chassis. Because these upgrades consist of changes to switch and line cards only, the system does not have to be taken off line."
Similar to a laser guidance system, Accelerant's intelligent silicon technology dynamically senses the inter-symbol interference of each backplane interconnect, then uses continuous feedback to guide and adjust equalization for optimum performance and most efficient use of power. Accelerant is unique in its ability to combine both traditional binary signaling as well as proven technology leadership in multilevel signaling (Pulse Amplitude Modulation or PAM-4) to pack two bits per clock cycle and double the data rate for a given clock speed. Its binary signaling mode has been carefully optimized to enhance robust interoperability with other SerDes devices.
Typical binary backplane transceivers operate with 25 percent overhead in the serial stream encoding. This consumes precious backplane bandwidth and requires the transceiver to understand individual coding protocols. Accelerant has developed technology that reduces signaling overhead to as low as zero percent, effectively enabling 100 percent bandwidth utilization across the backplane.
The 6000 series also feature a per-channel built-in programmable Bit Error Rate Tester (BERT), which can be used to continuously monitor the bit error rate of transmissions over each individual backplane interconnect with a level of confidence comparable with a $30,000 external BERT. This gives system developers the high level of reliability validation they need at these increased data rates, and highlights the inherent signal integrity of the technology.
Accelerant achieves its extremely low power consumption of <1 W for
a quad device through optimized adaptive equalizers and low power circuit
implementation. The low power facilitates use in dense circuit boards and
the technology's use in custom ASICs. At 25 Gigabits per Watt, system developers
can remain within the thermal budget defined by existing chassis design,
or integrate the technology onto high port count ASICs as offered by Agere
Systems through a previously announced partnership with Accelerant.
analogZONE Says . . .
Those folks at Accelerant are a bunch of troublemakers. The stuff I learned last year while reviewing their first 5/6.25-Gbit/s bus transceiver challenged enough of my beliefs that it was a major catalyst for starting the on-line debate about backplane SerDes technologies I hosted last fall. Once again this year, the ongoing discussions we've had about the merits of their multi-level signaling scheme versus conventional 8B/10B binary SerDes line coding helped inspire me to kick-off the "Equalize This!" Gigabit Backplane Challenge, a series of real-world lab tests that we're running in cooperation with Georgia Tech. And, once again, their new AN6425 is an example of how they're still re-thinking, and re-engineering the revolution that they started.
The AN6425, and the soon-to-follow AN6420 build on the AN5500's technology, but adapt it to meet what Accelerant has learned about the SerDes market over the past year. For one thing, the 642x series is intended to be line code-agnostic. While they have always supported binary line coding (or what they jokingly refer to as PAM-2), the big news is that they are now bringing the same advanced equalization and link management techniques they developed for PAM to the binary world. This allows their chip to run at optimum speeds on whatever backplane (or interconnect) medium they are asked to work in.
In truth, the first part in the series (the AN6525) will support only a subset of the PAM functionality in binary mode, but the 6420, due out later this fall will embraces both modes with equal fondness. They're not abandoning their PAM-4 system, but simply admitting it may not be the best solution in all applications.
As I said, the new transceiver family carries much of the technology developed in the 5000 series, including their proprietary adaptive equalization technology, and the ability for each Tx/Rx pair to use in-band signaling to autonomously adjust link parameters in real-time. The 6000 series adds quite a bit of functionality, including a sizable chunk of new features including:
This generation of products has migrated from the 0.25 micron process used to make the 5000 series to a 0.13 micron process -- and it's paid big dividends. Besides giving it more speed overhead, the chips consume much less power. For example, a quad SerDes running over 30 inches of FR-4 and 2 connectors, plus 8 channels of CML interface (system-side interconnect) draws under 1 W at 6 Gbit/s. Running at 10 Gbit/s it draws 1.4 W. I was skeptical, but Bill Hoppin, VP at Accelerant says this is what they're seeing in real-world systems in customer backplanes.
The extra equalization, speed margin, and power efficiency add up to great performance, supporting 5-Gbit/s across a 60 inch FR-4 backplane, and well beyond 60 inches at 3.125 Gbit/s. At shorter distances (20 inches), a reasonably-modern backplane can support 10 Gbit/s using PAM-4 mode, and they have the pictures to prove it.
Accelerant has also developed a way to do away with the line coding overhead that can eat up to 25% of a SerDes link's usable bandwidth. Dubbed "zero-percent overhead", the design does not require the traditional line codes (typically 8B/10B in 3.125 Gbit/s SerDes) that are added to guarantee dc balance and enough transitions to keep the Rx PLL locked. Accelerant uses a 2nd-generation scrambler that improves transition density, along with upgraded EQ and PLLs, to produce a system that locks and runs well without any line coding. This allows the chip to be "line code agnostic," and "pass through" any existing line code in a transparent manner.
This all adds up to an ability to extract more bandwidth from both new and legacy backplanes at a very reasonable cost/power ratio. Accelerant says they've demonstrated this in over 60 different real-world systems of all kinds, including finding useful SerDes channels in unused PCI bus trace pairs.
I think Accelerant's decision to focus initially in mining bandwidth from legacy systems is a smart move, With most companies living with severely limited capital equipment budgets, manufacturers will probably be doing a significant amount of their business in upgrades that expand the capacity and/or the features of the stuff they already have in the field.
These transceivers should enable manufacturers to offer upgrades for more, or faster, ports in the same chassis at much less than the cost of replacement -- while still turning a nice profit. For example, the DFE-based equalization allows the AN6425 to be dropped into an existing 622-Mbit/s backplane and instantly upgrade most, or all, channels to 3.125 Gbit/s -- without even using its PAM mode. This strategy will be a very useful strategy even in better economic times, since it allows customers to extend the life of their capital equipment from 4/5 to 10/12 years, while manufacturers still continue to sell profitable upgrades.
But dropping new silicon into existing systems requires it works in harmony with the entire "ecology" established within the box -- this includes backplane characteristics, existing power supplies, and thermal constraints. Accelerant is one of several companies who have positioned their products to meet all these requirements. They also understand that part of the ecology is the error budget allocated to each subsystem. In light of this they have included a very effective per-channel bit error-rate test (BERT) circuit that will help in both the design and manufacturing phase. It's even conceivable that a box's operational software could be designed to use the BERT feature to optimize channel parameters on the fly or, more likely, support sophisticated self-diagnostic features that reduce field service costs.
Besides finding a home in the sockets of upgrade line cards and switch fabrics, the AN642x series will enable new networking equipment to enjoy new levels of line density and power efficiency. I also see big opportunities for the transceivers in high-performance storage-area networking products, a market that is likely to see daylight much sooner than enterprise or carrier equipment. The transceiver's ability to shovel Gigabits down lengths of twisted-pair or co-axial copper cables lends it to lots of short-haul box-to-box interconnect applications as well. I've seen earlier chips supporting full-speed connections over low-cost InfinBand cables, something that might allow products employing the popular "stackable pizza box" switch form factor to support much higher bandwidths.
Accelerant is sampling the AN6425 now. It focuses on PAM applications and does not have full range of binary line code operation. The pin-compatible 6420 will be available in late fall of this year and will support the full suite of binary transmission features.
Pricing for both parts in 1000-piece quantities will be around $90.
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