i/oZONE Products for the week of June 28, 2004
Xilinx Says…
Beyond Vanilla: XILINX's VIRTEX-4 Family Embeds Application-Specific
Mixes Of Hard-Wired Logic, Processors, and I/O For Space And Cost Savings
Xilinx, Inc. has unveiled details of its Virtex-4 Platform FPGAs, the fourth generation Virtex product. Enabled by the revolutionary Advanced Silicon Modular Block (ASMBL) architecture, the Virtex-4 product line is the world's first FPGA family with multiple domain-optimized platforms, offering breakthrough FPGA capability at every price point. The initial Virtex-4 family includes three platforms; Virtex-4 LX for logic, Virtex-4 SX for very high performance signal processing, and Virtex-4 FX for embedded processing and high-speed serial connectivity. Each platform will offer a range of device options. With up to 200,000 logic cells and up to 500 MHz performance the Virtex-4 family delivers twice the density and up to twice the performance of any FPGA in the industry currently in production.
Leveraging the proven success of the Xilinx Virtex series and the company's one-year lead in 90nm process technology, the Virtex-4 family is poised to move beyond the $5.1B programmable logic market to capture additional share in the $36B ASIC and ASSP markets. System designers within high-growth technology segments such as wired and wireless communications, storage and multimedia will now be able to use cost-effective FPGAs for applications previously served only by ASICs and ASSPs.
"By exploiting the unique advantages of the revolutionary ASMBL architecture, the Virtex-4 family delivers the highest level of performance, density and feature integration of any FPGA on the market today," said Wim Roelandts, president and CEO at Xilinx. "This powerful combination offers a cost-effective alternative to ASICs and ASSPs and positions us well for continued growth into applications previously served by these types of devices."
One Family -- Multiple Platforms
The Virtex-4 family is the first embodiment of the revolutionary ASMBL architecture,
a design methodology that enables Xilinx to rapidly and cost-effectively
assemble multiple domain-optimized platforms with an optimal blend of features.
This multi-platform approach allows designers to choose an FPGA platform
with the right mix of capabilities for their specific design. Features such
as the logic fabric, block memory, clock management, and the XtremeDSP slices
are all performance matched to support up to a record-breaking 500 MHz clock
speed. By reaping the benefits of advanced 90 nm process technology and
the innovative architecture, the family's logic capacity ranges up to an
unrivaled 200,000 logic cells.
Virtex-4 Family Overview
The Virtex-4 LX, SX and FX platforms each provide a different mix of core
capabilities, such as logic, memory, parallel and serial I/O, embedded processors,
high-performance DSP functionality, enhanced clock management, hard IP,
mixed signal, and other function blocks suited to specific application requirements.
Virtex-4 LX Platform FPGAs are assembled for general logic applications and offer the highest logic density and most cost-effective high-performance logic and I/Os. Members of this family provide abundant logic cells together with embedded Block RAM, digital clock management (DCM) blocks, and XtremeDSP/arithmetic functions to handle high-density, I/O intensive, and high-performance logic applications across multiple markets. The Virtex-4 LX programmable devices redefine FPGA capability-cost ratios and deliver the industry's highest value FPGAs ever.
Virtex-4 SX Platform FPGAs are assembled for high-performance signal processing applications such as wireless communication, video, multimedia and advanced audio. Members of this family offer all the capabilities of the LX platform and are designed for very high-performance real-time signal processing with an exceptionally high ratio of XtremeDSP slices and embedded Block RAM. The highest XtremeDSP-slices-to-logic and embedded Block RAM-to-logic ratios allow the Virtex-4 SX programmable devices to offer breakthrough DSP performance at significantly reduced power consumption compared to alternative FPGA solutions. In addition, the 500 MHz XtremeDSP slices can be cascaded and operate at full system speed.
Virtex-4 FX Platform FPGAs are assembled with capabilities tuned for complex system applications including high-speed serial connectivity and embedded processing, especially in networking, storage, telecommunications and embedded applications. Members of this family offer the industry's first multi-gigabit serial transceivers supporting any speed between 600 Mbps and 11.1 Gbps, enhanced embedded PowerPC 405 processors with an auxiliary processor unit for hardware acceleration, in addition to abundant logic cells, block RAM, DCM clock managers and DSP/arithmetic functions. By offering built-in capabilities for complete system integration, Virtex-4 FX programmable devices provides the most advanced Platform FPGA available for system design.
Building on Proven Success of the Virtex Series and Process Technology
Leadership
Virtex-4 Platform FPGAs are the fourth generation of devices in the Virtex
Series. Since its 1998 introduction, the company has shipped over 10 million
Virtex devices. Generating nearly $2.5B in cumulative revenue, the Virtex
family has significantly contributed to the company's record-breaking gains
in PLD market share for six consecutive years. Based on their industry-leading
capacity, performance, and cost-effectiveness, Xilinx Virtex FPGAs are the
number one choice of designers worldwide. Thanks to consistent development
of design tools, FPGA architecture and system capabilities, customers and
partners are able to leverage existing IP investments for new designs in
Virtex-4, with significant performance, power and pricing advantages.
ASMBL Architecture Overview
The new ASMBL architecture is a modular framework of silicon subsystems,
enabling Xilinx to rapidly and cost-effectively deploy platforms targeted
to different application domains. Each domain includes a variety of applications
sharing common requirements such as very high-performance signal processing,
embedded processing and high-speed connectivity. As a result, customers
can select the platform with the optimal mix of features and capabilities
for a specific design. The ASMBL architecture makes use of advanced flip-chip
packaging technology eliminating geometric layout constraints associated
with traditional chip design such as hard dependencies between I/O count
and fabric array size. The architecture also addresses the increasingly
more stringent requirements for on-chip power and ground distribution by
allowing power and ground to be placed anywhere on the chip. As a result,
Xilinx can significantly accelerate development time, reduce cost and increase
reliability for designers using FPGAs.
analogZONE Says . . .
Although FPGAs are on the fringes of my usual coverage, the newer generations of these devices are becoming more specialized, with so many high-performance I/O and even some networking capabilities that they really need to be considered as communication or I/O products. Xilinx's recent announcement is an excellent example with the release of a product line that offers custom feature sets for specific application areas and embeds some really sophisticated I/O elements along with the normal sea of gates. This tightly-targeted approach, plus a more space-efficient device architecture that helps reduce the size of the chip makes this family of devices become a cost-effective solution in applications where FPGAs were previously considered too expensive.
Part of the overall real-estate savings is accomplished using "striped" columns within the chips that have function-specific blocks of hard-wired logic, memory, clock management elements, and DSP blocks placed in strategic locations throughout the floor plan. Each family uses different proportions of each element that are best suited to a particular kind of application. Their first offerings include the LX family, which is architected for implementing lots of high-speed logical and clock distribution functions, and the SX series which is intended for DSP/signal processing. The latter should prove extremely useful for baseband and voice processing applications, allowing quick development of everything from IP voice gateways to wireless infrastructure equipment.
Both the SX and LC families are equipped with a good mix of hardwired I/O to save you the trouble (and the gates) of "rolling your own," but the FX series seems to be the device of choice if you need raw connectivity. Xilinx intends the FX as is a general-purpose chip that contains lots of logic cells, block RAM, DCM clock managers and DSP/arithmetic function, but it is the only one to boast hardware RISC processors (PowerPC 405 cores), and multi-gigabit serial and parallel transceivers. The SerDes channels can support any speed between 600 Mbit/s and 11.1 Gbit/s, while the parallel interface runs at up to 600 Mbit/s in a single-ended mode and 1 Gbit/s using differential signaling.
Xilinx provides additional cost savings for high-volume applications with its EZ Path program. Since testing constitutes a significant portion of the cost of an FPGA, Xilinx will allow you to buy devices that are tested for only the elements in use in your design at a discounted price.
About the only cautionary note I'd sound here is that Xilinx's claims for their interface speeds are true, but with some very real limitations. Although they have done a good job, you cannot expect the high-speed interfaces embedded in these devices to have as much performance margin as some of the transceivers I've seen in other products, especially standalone transceiver chips. Their recently-announced 10-Gbit/s SerDes technology certainly does work, but it has some significant limitations in reach unless you use sophisticated connectors and PCB material that affords better dielectric performance than ordinary FR-4 board. Xilinx has worked closely with Winchester Electronics and other manufacturers on its UXPI 10-Gbit/s initiative. Together, they have produced a very respectable 10-Gbit/s backplane reference design that uses Winchester's SIP1000 connectors, and a high-dielectric PCB material.
I'm still undecided as to whether most applications will be better served using more sophisticated silicon to drive 10-Gbit/s over "vanilla" FR-4 backplanes, or if it's more cost-effective to employ premium backplane materials and manufacturing techniques. Most likely there is a sizeable market niche for the latter, but I'd expect that for many applications running multiple 2.5- or 5-Gbit/s channels (using Xilinx or other transceiver technologies) over more conventional backplanes should prove a good interim solution for many applications.
Since Xilinx is very committed to not announcing specific products until there are parts "sitting on distributor's shelves," they are not releasing data sheets or pricing until some time later this summer, or earlier this fall. Initial engineering samples of the Virtex-4 LX Platform FPGAs will be available in Summer 2004, with SX and FX platforms to follow. EasyPath support will be available at the time of production. General design tools support will also be available in summer 2004.
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