connectivityZONE Products for the week of May
1, 2006
Altera Corporation Says…
Altera's Stratix II GX FPGAs & Signal Integrity
Development Kit Enable SerDes Without Tears
Both devices and development kit available immediately
Continuing to provide developers of high-speed applications with an
efficient, low-risk design path, Altera Corporation has begun shipping its
Stratix II GX EP2SGX90E device and accompanying development kit. Featuring
12 transceivers and 90,960 equivalent logic elements (LEs), the EP2SGX90E
device is the first member of the Stratix II GX FPGA family to ship to customers.
"Our EP2SGX90E FPGAs provide high-speed designers with an award-winning
90-nm device with embedded transceivers," said David Greenfield, Altera's
senior director of product marketing for high-density FPGAs. "Altera
is the first in the industry to deliver the port density, transceiver speed
and optimized jitter performance that the Stratix II GX family offers. Our
rigorous methodology of building test chips and using stable fabrication
processes and device models enables us to continue our track record of early
or on-time delivery of our 90-nm FPGA families."
Development Kit Simplifies and Accelerates Customer Design Process
The Stratix II GX signal integrity development kit is the ideal platform
for evaluating and validating the signal integrity features of the 6.375-Gbit/s
transceivers. This development kit provides everything necessary for the
validation of high-speed backplane interface, chip-to-chip and communications
protocol-bridging applications. It includes configuration options, flexible
clocking options and a USB port to interface with a PC for easy plug-and-play.
analogZONE Says . . .
Since I reviewed Xilinx's handy little PCI Express
starter kit last
week, I thought Altera deserved equal time for its excellent SerDes signal
integrity evaluation kit. Besides providing a showcase for its previously-reviewed
Gigabit SerDes-powered Stratix II GX FPGAs, the kit should be a big help to the many digital engineers
who must now deal with the analog-intensive design issues associated with
high-speed serial interfaces such as XAUI, PICI Express, Gigabit Ethernet,
XAUI, CEI-6G, Serial RapidIO, or HD-SDI.
The
board serves as a nice little test bench on which you can exercise one or
more of the FPGA's integral six full-duplex SerDes transceivers on one of
several different on-board channel environments they've provided. You can
program any one of the transceivers for speeds of 622 Mbit/s to 6.375 Gbit/s
and route them to the desired trace using simple SMA cabling to get a feel
for how the signals behave in microstrip or stripline environments (see
Fig. 1).
If you're investigating multi-lane SerDes-based busses like PCIe or SRIO,
you'll really appreciate the four stripline channels they provide from the
same transceiver quad that has all the trace lengths matched across channel.
The kit even has one channel with a 40-inch PCB
board trace length on the transmit side and a 10-inch board trace length
on the receive to simulate the degradation associated with backplanes or
long traces. And if you have a specific application in mind, you can bring
your signals out via the boards integrated SMA connectors to bring hook
them up to your own backplane, motherboard, or other target system.
Altera
has gone out of its way to give you everything you need to start fooling
around with SerDes. All you'll need to bring to the party is a PC which
you'll use to program and run the FPGA via a USB port. The test software
presents an easy-to-use GUI control panel which allows you to set the speed,
data patterns and channel compensation parameters for each SerDes lane without
having to get deep inside the chip and twiddle with binary registers. Both
SerDes novices and grizzled veterans will appreciate how easily the knobs
on the GUI interface (see Fig.
2) allow you to adjust each channel's three transmit
pre-emphasis parameters (1st and 2nd post-tap and precursor) and output
its differential voltage. Each channel's two-stage receive equalizer can
also be easily adjusted using the graphic interface.
About the only shortcoming I was able to spot is
that the Stratix FPGA's receivers do not have a tap on the receiver available
for viewing the traditional data "eye," often used as a way to
get an empirical sense of the signal's integrity. Altera has provided an
alternative method that uses the GUI software to display both a BERT reading
and an error ratio slope figure for each channel. They say that their customers
have found that the combination of BER and error ratio slope readings give
them the feedback they need to tell whether adjustments to a channel's PE
and EQ settings are improving or degrading its performance, and whether
they are moving towards or away from an optimal setting.
In spite of this, I'd still strongly encourage
Altera to find some way to provide a receive eye pattern in their next generation
of chips and eval boards because eye diagrams can often reveal many subtle
signal integrity issues to the trained eye that will not be visible on the
simplified statistics they currently provide. Nevertheless, I give them
high marks for coming up with such a simple and helpful tool for tuning
their transceivers.
According to Altera they've watched some of their
early adopter customers use this simple, inexpensive board to quickly tune
the FPGA transceivers to provide optimum signals for their own backplanes
and circuit boards -- often within a day or so of opening the box. And from
what I saw on a recent lab visit to see an early version of the evaluation
system, I think that it's a credible claim.
The kit, available for $1295, also includes QuartusII
design software, an ac adapter power supply, a USB-Blaster download cable,
two SMA-compatible cables, reference designs and documentation. The EP2SGX90E
is shipping now with the EP2SGX90F -- featuring 16 full-duplex high-speed
transceivers shipping in June 2006.
Data Sheet: Stratix II GX
FPGA Family
analogZONE
(c) 2006. All rights reserved.
