i/oZONE Products for the week of April 5, 2004
Analogix Semiconductor Says…
Analogix' 6.25Gbits/s Backplane SerDes Features Adaptive
DSP-Based Noise Cancellation
Advanced Analog+DSP Architecture Enables FR-4 Backplane Upgrades
To 6.25Gbits/s;
Later Products Will Facilitate System Interconnect Over Low-Cost Copper
Analogix Semiconductor has introduced the first high-speed physical-layer
transceivers that incorporate digital signal processing (DSP) techniques
to eliminate the signal integrity ("noise") problems associated
with 5- and 10-gigabit-per-second data transmission over backplanes and
copper media.
The D-PHY family of SerDes ICs is based on a new architecture that combines Analogix's WideEye technology - a set of adaptive DSP-based noise-cancellation techniques - with advanced analog signal conditioning. Unlike analog-only solutions, which simply mask detrimental signal effects such as crosstalk and reflections, the D-PHY family actually removes these effects, ensuring maximum signal integrity.
With noise problems eliminated over standard FR-4 backplanes and very-short-reach (VSR) system-to-system copper interconnects, system designers can:
The D-PHY family is designed for use in enterprise switches and routers, carrier-class transport equipment (including optical switches and cross-connects), Fibre Channel and IP-based storage systems, and high-end servers.
The first D-PHY products, D-PHY 5G backplane transceivers, are being announced today. A 10-Gbits/s serial backplane transceiver family and a 10-Gbit/s serial interconnect over copper IC family will be introduced later this year.
Analog-only Approaches Can't Handle Noise Issues at High Speeds
Ted Rado, vice president of marketing at Analogix, said, "The ubiquitous
copper-based FR-4 backplanes in today's systems were designed when speeds
of 5 Gbits/s and above weren't even imagined. Now designers of switches,
servers, storage arrays and the like want more performance, but they want
to get it by upgrading, not replacing, their existing systems. As vendors
try to design new high-speed cards that fit into old FR-4 backplanes and
interoperate with existing cards, they face major noise issues that analog
techniques can't handle - not just signal attenuation but crosstalk and
reflections. Since the backplane itself has a fixed number of traces, the
burden is on the silicon to deal with the increased noise while pushing
more performance through those traces.
"The same issues surface in system-to-system interconnect, where, even at distances of under 50 meters, copper media have severe noise issues at speeds over 1 Gbits/s," Rado added. "Thus far, expensive, power-hungry fiber solutions have been the only choice."
D-PHY Architecture: Adaptive DSP Signal Conditioning Joins Advanced
Analog Techniques
Analogix's solution is the D-PHY architecture, an advanced analog/DSP-based
approach that maximizes signal-conditioning flexibility. Like traditional
analog-based SerDes technology at 3.125 Gbits/s and below, D-PHY devices
offer standard transmitter-programmable pre-emphasis and swing control.
Up to now, companies targeting speeds beyond 3.125 Gbits/s have incorporated
more advanced analog receive-based equalization, typically in the form of
Decision Feedback Equalizers (DFEs). The D-PHY architecture's two chief
elements - one analog, one DSP - offer significant advantages over such
approaches:
D-PHY 5G Product: 6.25 Serial Performance on an FR-4 Backplane
The D-PHY 5G backplane transceiver offers 1.25- to 6.25-Gbits/s serial transmission
across up to 60 inches of standard FR-4 backplane material and two connectors.
Two versions are available. The D-PHY 4x5G quad transceiver, with four high-speed
links, provides up to 25 Gbits/s full-duplex transmission. The D-PHY 2x5G
dual transceiver, with two links, performs at up to 12.5 Gbits/s. NRZ binary
encoding on both devices ensures backward-compatibility with lower-speed
SerDes transceivers. All D-PHY devices are compliant with the Optical Internetworking
Forum's Common Electrical I/O (CEI) 6G+ specification.
Each D-PHY device also has eight low-speed (800 Mbps-3.125 Gbits/s) SerDes
links. Flexibility is increased by three multiplexing options: 1:1, 2:1
and 4:1; a unique legacy mode available with 1:1 multiplexing detects connection
with another SerDes device (e.g., a XAUI transceiver), allowing new cards
to interoperate with existing ones. Comprehensive built-in self-test (BIST)
functionality includes on-chip PRBS generators and error checkers as well
as low- and high-speed loop-back paths for independent testing of all chip
elements. D-PHY devices also offer real-time bit error rate (BER) monitoring
capabilities by polling MDIO- or I2C-controlled WideEye DSP registers.
analogZONE Says . . .
With the anticipated surge in bandwidth demand in everything from enterprise routers to broadband data services, the multi-Gigabit backplane silicon market has certainly become one of the hot topics in the industry. And with the anticipated demand for silicon that can mine bandwidth from lower-cost, FR-4 based backplanes, we're seeing a crop of new chip makers popping up like mushrooms after a rainstorm. Analogix is not quite a typical example of this since these folks have been around for around two years and are only "de-cloaking" now that the market has matured a bit. They're also somewhat unusual since they have come on the scene with working products and several serious Asian customer wins in-hand.
Analogix is bringing to bear the technical know-how inherited from their years at Conexant's HotRail group and Marvell's networking product line on the challenges of creating backplane transceivers that target a variety of applications which need to carry 5 to 10 Gbit/s across inhospitable channels. These include "inside the box" serial backplane interconnects and "outside the box with 10G over Infiniband and Cat-5/6 copper (a play to replace costly VSR optics). The D-PHY 5G backplane transceiver reviewed here is among the first of a series of product that will use their unique hybrid architecture to solve some of the pesky problems that SerDes designers are facing as they migrate to higher speeds.
Analogix took a clean break from existing SerDes technologies, rather unlike those companies that build faster versions of their existing 1.25 and 2.5 Gbit/s product lines. This makes sense to me because it's becoming apparent that the relatively simple pre-emphasis and equalization schemes that work well for 3.125 Gbit/s begin to run out of gas, and must be supplemented by adaptive equalization, and dare I say it, cancellation techniques. If you simply build on an existing architecture, this inevitably leads to more silicon per channel and, often, more power as well.
These transceivers avoid this by segmenting the signal processing tasks between analog and digital DSP elements to let each element do what it does best. They use an analog section to do the heavy equalization before passing it to a pipelined DSP element for some additional EQ as well as all the echo and cross-talk cancellation.
Taking a look at the analog section first, we see that the receiver EQ uses something called a multistage, continuous time linear equalizer (CTLE). As the name implies, it employs continuous sampling and does not require a feedback path like the decision feedback equalizers (DFEs) traditionally used in these kinds of receivers. Since I am not an expert on equalizers I'll have to take their word that they are able to use a feed-forward EQ with a low-speed feedback loop to eliminate the power-hungry DAC and feedback equalizer used in a DFE. The CTLE does its job by creating a summing of the EQ and slicer outputs and generating a non-real-time signal that is used to adjust the taps in the EQ. Analogix claims that this allows it to do the same thing as a DFE with much less silicon and power.
Like most other SerDes chips, the transmitter has a programmable pre-emphasis capability that can be used to boost high-frequency components to get through especially lossy runs. For the most part, however, Analogix says that it's better to avoid using it because it adds to crosstalk in adjacent channels -- especially in "problem" channels found in legacy systems.
In fact, for many channel traces, the chip's CTLE analog equalization alone is enough to clean up a signal to achieve a clean clock and solid data recovery. But if you have a really dirty signal due to excessive reflection, crosstalk, or other interference, you can pass the signal through some or all of the DSP block to perform the necessary cancellation, as well as supply some additional equalization.
This ability to selectively engage signal processing blocks is a very nice feature that lets you turn off any unneeded blocks for big power savings. Designers can mix and match features on a per-channel basis as needed. If you have a well-behaved backplane you can run a quad-channel transceiver in as little as 2.9 W. Full-up operation is not too bad either, at just around 5.5 W.
But even if you can design a DSP to handle the necessary processing at 5 Gbit/s there is a big challenge involved with getting an ADC fast and accurate enough for this speed. I discussed this in depth with Jianbin Hao, Analogix's VP of product development, and he was reasonably candid about the difficulties they encountered and the solution they found. While I cannot divulge the particulars of what I learned, their approach seems very credible. This, coupled with the results I saw in their lab (I told you they had silicon!) indicates that this chip will perform as advertised.
Given what I've seen, I think they are quite able to deliver on their claims of sending 6.25 Gbit/s over four connectors and 60 inches of FR-4. Happily, the same signal processing techniques also work wonders on other difficult copper-based channels, like Cat-5/Cat-6 UTP and Infiniband cabling. While their current device does not do this, I can attest to seeing closely-related products in their lab that do. The next part will be compliant (and exceed) CX-4 standards requirements.
Another interesting thing to note is that Analogix says that its technology is just idling over at 6.25 Gbit/s, rather than straining to keep up like the stuff adapted from 3.125 technologies. This should give you more than a hint that they intend to move into higher speed applications as the market demands it.
The D-PHY 5G is sampling in HSBGA-260. Production will be June 2004 with pricing starting at $28 in high volumes.
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