i/oZONE Products for the week of April 22, 2002
Accelerant Networks says . . .
Accelerant Networks Sampling The Industry's First
5-Port, 6.25 Gbit/S Backplane Communication Transceiver
Accelerant Networks Inc., is now sampling the AN5500 backplane communications
transceiver, the first chip to integrate 5 ports of up to 6.25 Gb/s full-duplex
transceivers operating over 48" of FR4 and connectors. Proven and tested
in production environments, including over 30 existing and new backplanes,
the AN5500's unprecedented combination of per-channel adaptive equalization
and multi-level signaling have set a new standard as the essential building
blocks for 6.25 Gb/s backplane transceivers. The AN5500 is currently being
sampled by a number of the leading communications equipment companies and
will be in full production in Q3, 2002.
"With Accelerant's advanced backplane communication technology, we
have created a key solution for the development of high performance communication
equipment", said Paul Nahi, President and CEO of Accelerant Networks."
The AN5500 is well positioned to become a de facto standard for the development
of next generation backplanes at the heart of tomorrow's networks."
Multi-Channel Adaptive Equalization
The AN5500's key to optimal performance on every backplane is continuously
adaptive equalization on each channel. By characterizing each channel, adjusting
the amplitude, and continuously adjusting the equalization during operation,
the AN5500 is able to achieve from 3.125 up to 6.25 Gb/s per channel under
varying conditions. Unique trunking features of the AN5500 provide seamless
aggregation of the total bandwidth with no external logic required. Furthermore,
multiple AN5500 devices can be locked to deliver payloads in excess of 240
Gb/s in each direction. Having proven the robust multi-channel capabilities
of WILDPHYR backplane communication intelligence-continuously adaptive equalization,
multi-level signaling, and auto-negotiation-Accelerant is working with strategic
partners to integrate higher port-count application specific solutions.
Faster Time To Market
Today's systems require greater reliability as well as higher performance.
The AN5500 includes a pseudo-random bit sequence (PRBS) generator and detector.
In combination with near-end and far-end loopback modes, this feature enables
the user to test channels during development and debug, as well as the production
phase. The need for external equipment to test signal integrity is eliminated.
Critical Insight Into The Complex Backplane
Unique to Accelerant's WILDPHYR technology is the ability to provide insight
into the inner workings of the backplane during the development process.
The AN5500 comes with an easy to use GUI that interfaces with the automatic
channel characterization hardware built into the chip and provides a virtual
window into the channel. The software enables backplane optimization and
characterization during the debug and manufacturing processes and speeds
the test and evaluation of complex designs. Never before has the developer
been offered this level of access to channel information at such a critical
phase.
Extending The Product Line
The AN5500 extends Accelerant's backplane communications transceiver product
line launched in July with sampling of the AN5000. Utilizing WILDPHYR technology
as the essential building block of robust 6.25 Gb/s transmission, already
proven in numerous existing backplanes, the AN5500 offers customers a higher
density solution for switch cards or systems demanding higher aggregate
bandwidth. Enabling high-speed chip-to-chip connections, the AN5500 features
high-speed connections to ASIC devices, using LVDS I/O operating at 311
to 625 MHz DDR.
Wildphyr Technology
The continuously adaptive equalization, multi-level signaling and auto-negotiation
of the AN5500's WILDPHYR backplane communication intelligence optimizes
performance, improves ease-of-design, and increases reliability in new and
existing networking equipment. Because Accelerant Networks' WILDPHYR technology
was developed specifically to solve the bottleneck problem in backplanes,
it opens up more options for developers of networking equipment than ever
before. The AN5500 is proven to deliver next-generation channel speeds on
existing systems, as well as those under development.
analogZONE Says . . .
Pent-Tastic! Accelerant's 6.2 Gbit/s Backplane Transceiver Now Comes In a 5-Pack
When I first talked with Accelerant a year go, I was more than a little skeptical at their claims of a 5-Gbit/s multi-level coded backplane transceiver. But when I asked all the hard questions and they gave me straight answers, I was sufficiently convinced that they had a chance at delivering working chips to do a first product review. Then in late January of this year, my faith was rewarded with a hands-on demo of their 1-port transceiver operating at 5 Gbit/s under real-world conditions. I was told that several customers had initially dismissed MLT and adaptive equalization technologies, but are now coming back because they realize that at or beyond 5 Gbit/s, MLT and equalization are essential.
Just as the glow from this first success is fading, Accelerant has rolled out the AN5500, a 5-port transceiver - and this time it's running at speeds of up to 6.25 Gbit/s. Accelerant has upped the speed in part, to provide the extra overhead needed for systems that employ forward error correction. The current crop of 3.125 Gbit binary SERDES chips will take twice the number of channels to support a nominal 10 Gbit/s connection, but Accelerant expects that manufacturers will start shipping 6.25 Gbit binary SERDES chips to sample by the end of '02. This gives Accelerant a 1-year window to win as many customers as possible before 6.25 Gbit/s SERDES catches on in the market. Accelerant is also counting on the fact that it will take lots of work to make 6.25 work anywhere close to 3.125 Gbit/s (in terms of reach and noise immunity.)
Quite frankly, I was amazed at their single port part, and I'm still trying to get my head around how they managed to put five of these transceivers on the same piece of silicon. In discussing this development with Accelerant, I was told that the transceiver was reasonably compact despite its complex pre-emphasis and equalization scheme because it makes extensive use of analog processing techniques (fewer digital gates.) This allowed them to put the five channels on a medium-sized chip using existing .25 process geometry even before they migrate to a .13 micron later this year.
Part of the success is due to the fact that they do everything in house, from IC design, packaging, and signal integrity, to layout and product test. It must be a good strategy, because both products worked on the first spin. The AN5000, which sampled in Dec '01, is in full production now, while today's AN5500 is in pre-release. Accelerant anticipates production runs for the '5500 in Q3 '02.
They've also added a new capability that allows for channel synchronization and aggregation of the chip's serial channels into a single, fat, 30 Gbit/s pipe. If you have a really burning need for an even larger chunk of bandwidth, you can also tie together multiple chips for a single channel with a total capacity of up to 200 Gbits. You can feed each channel via a system interface that connects to a MAC or framer using a 1.25 GHz 4-bit parallel LVDS connection. This is double the speed of the single-channel 5000's previous 8-bit interface. The new 4-pin interface helps keep the pin count down for multiple connections and extends reach (8") between chips.
All five receivers have their own adaptive EQ system. Each transceiver also has its own independent CDR and PLL systems. Since possible inter-channel interference worried me, I was relieved to hear that the transmitters incorporate an adaptive transmit level function. By monitoring the channel's BER as the transmitter adjusts its signal levels, it is able to find the lowest amplitude required for a robust link. This can really help minimize cross-talk and ISI, as well as unnecessary internal signal levels that could potentially bedevil sensitive PLLs. I suspect that this is not all there is to the matter, since I've heard real horror stories from a couple of binary SERDES transceiver makers about their first attempts to put multiple channels on a single chip.
Like the single port device, the new part offers adaptive equalization, PAM signaling, and continuous back-channel auto-negotiation to deliver reliable high performance. Surprisingly, Accelerant is finding that the adaptive EQ technology is providing an unexpected bonus for some of its customers. It seems that most designers are finding that they can re-use their existing 1.25-2.25 Gbit serial backplane designs with no changes, and more than double capacity of many popular networking products. Although the double-rate requires accelerant at both ends of the line, the transceiver's dual-mode operation allows it to fall back to an 8B10B coding mode that lets it interoperate with most existing half-rate binary SERDES transceivers. This lets your equipment work with old binary SERDES cards and new PAM MLT cards for painless upgrades to legacy applications.
Accelerant has also developed new software drivers that allow designers and test engineers to use the chip to characterize backplane performance. The program, run on a plain-vanilla PC, allows parametric measurements to be collected in a real-world environment. By letting engineers use the chip's JTAG port to collect the BER information on any, or all channels, it's relatively easy to tease out performance margins available for specific channel conditions. You can change supply voltage, temperature, and backplane manufacturing process to obtain realistic performance margins for a given design. This can insulate your design against changes due to process variations, design issues, or change of mfr.
And speaking of variable conditions - using a transceiver with adaptive EQ means that there are no adjustments or tweaks required when systems are manufactured or field serviced.
In keeping with the behavior of their previous one-channel device power consumption is modest - They've measured it at 800 mW per channel for a maximum of 4 W total, and even less when some channels are not used or running slower.
So, once again, Accelerant has come through on its almost unbelievable claims. With so many channels on a single chip, I still have some concerns about potential problems with CDR errors and inter-channel interference in maximum-reach applications, but am reasonably confident that these won't be crippling and that they can be addressed with a spin or two of the silicon. One thing that will help boost my confidence is a hands-on demo like the one I saw for the AN5000. They are doing demos at NGN, Supercomm, and other selected venues, so I can't wait to get to Atlanta this June.
The AN5500 5 x 6.25 Gb/s backplane communications transceiver is sampling
now in a 23 x 23 mm BGA-484. Volume pricing will be $220 in 1000-piece lots.
Evaluation boards, software, models, and application notes are available.
|