i/oZONE Products for the week of April 15, 2002
TriCN says . . .
TriCN's SPI-4 Phase 2 I/O Interface Offers Significant
Performance and Reliability Advantages
TriCN, a developer of intellectual property (IP) for high-speed I/O interface technology, has made available a new interface solution that delivers performance and reliability levels well beyond the compliance requirements for the System Packet Interface (SPI)-4, Phase 2 specification. This high-speed interface is a standard advanced by the Optical Internetworking Forum (OIF) for interconnection of physical devices at 10 Gb/s (OC-192) aggregate data rates and higher. TriCN's solution targets Taiwan Semiconductor Manufacturing Company's (TSMC's) 0.18 mm and 0.13 mm processes.
"As the development of high-performance networking and telecommunications equipment continues to heat up, there's escalating demand for new I/O interface technology that can take full advantage of OC-192 data rates," explains Ron Nikel, CEO and Chief Technology Officer with TriCN. "Communications systems designers not only need to meet the throughput performance of OIF's SPI-4 specification - particularly the Phase 2 version of the standard - but go well beyond the minimum thresholds to establish a key competitive advantage. TriCN is providing the enabling technology to deliver this competitive advantage with the introduction of its SPI-4 Phase 2 I/O interface solution."
Interface-Specific I/O
TriCN's new SPI-4 Phase 2 interface solution leverages the company's unique
interface-specific approach to I/O, which gives its customers a significant
implementation edge. Designers looking for a specific I/O interface find
that most suppliers deliver a solution for a generic I/O interface technology,
such as low-voltage differential signaling (LVDS). This leaves the customer
engineer acquiring such a generic solution with the tedious, time-consuming,
sometimes daunting, task of tailoring the generic solution to their specific
application. TriCN, by contrast, delivers LVDS in specific interface types
- in this case, SPI-4 Phase 2.
Interface-specific I/O is TriCN's unique approach to distinguishing its menu of targeted interfaces from what's available from other I/O IP providers. "The work we've done to produce interface-specific solutions frees up our customers from having to take on additional engineering tasks which not only impacts resources, but time-to-market," says TriCN's Nikel.
The SPI-4 Phase 2 interface solution consists of a transmitter hard macro (TX-SPI4), a receiver hard macro (TriDL-SPI4) and SPI-4 low-voltage differential signaling (LVDS) I/O's. These interface macros and input/output (I/O) solutions provide up to 24Gb/s aggregate data rates, to meet even the most aggressive throughput requirements.
TriCN's modular approach to the SPI-4 interface allows customized SPI-4 solutions, using either static or dynamic alignment, to be implemented seamlessly. This modular approach, combined with a core-side interface bus that can be programmed to be 64 or 128 bits wide, allows for straightforward integration of TriCN's SPI-4 Phase 2 solution.
This new I/O solution employ's TriCN's unique (patent-pending) approach to skew compensation, for maximum skew tolerance and unprecedented maximum throughput levels. In dynamic alignment mode, it provides bit-level de-skewing capable of handling skew levels up to +/- 2UI at 1.5Gb/s.
TriCN's SPI-4 Dynamic Alignment solution is a fully digital implementation. As a result, designers can potentially realize up to a 20% savings in silicon area, over a comparable delay-locked loop (DLL) implementation.
Signal Integrity and Timing
Application of TriCN's rigorous signal integrity and timing (SIT) analysis
ensures optimal and reliable performance of the interface. Each SPI-4 Interface
I/O and hard macro is qualified for timing completeness and signal integrity
quality for a full range of PCB impedance, PCB route lengths, terminator
tolerance, and topology for given operational frequencies and memory sizes,
assuring optimal and reliable performance. Delivery includes system layout
application notes, as well as comprehensive information for board layout
of the pads and pcb and interconnect subsystem. The HSPICE analysis environment
is also provided, so customers can perform further analyses as modifications
are made to the system.
analogZONE Says . . .
Doing Their Homework - TriCN's SPI-4.2 Interface IP Core Employs Meticulous Analog Design
Although backplanes, I/O channels, and other board-to-board interconnects remain a major bottleneck in multi-Gigabit designs, chip-to-chip speed issues are creeping upon us on cat's paws. One of the companies far-sighted enough to have solutions ready at hand is TriCN, a design house-turned IP vendor. Their latest development, an SPI-4.2 high-speed parallel interface has also found its first (publicly announced) customer with Internet Machines, a highly capable, OC-192-rated network processor reviewed in the networkZONE area of this web site.
Although originally intended as a media-independent interface for 10-Gbit/s applications, SPI-4 is becoming a widely-accepted chip-to-chip connection of choice between network processors, traffic managers, (in-line)classifiers, and other high-speed networking elements. It's good then, to see such a robust solution available on the open market. Such solutions seem to be TriCN's stock-in-trade.
Whether it's for QDR SRAM, PCI-X, or Infiniband, TriCN has quietly been turning their in-depth expertise in mixed-signal designs into a variety of licensable cores for memory, bus, and I/O interfaces that have been used by the likes of Apple, MIPS, Nokia, and SGI. Upon hearing this I was tempted to ask the obvious - why these firms, and even silicon experts like IBM and Philips, who have tons of expertise in this area have turned to a relatively unknown company to solve their tricky I/O problems? The short answer is that they have done their homework, and solved lots of nagging issues that stumped even the big guys.
The long answer is that TriCN has made a career out of modeling the behavior of mixed-signal interfaces, and not just the silicon. Instead of simply modeling their device around an idealized version of the chip they expect to see at the other end, and leaving it at that, they have spent a bunch of energy looking into the real-world conditions it will see. This model includes the characteristics of packages, connectors, printed circuit boards, vias, and the complex impedances that they create at the edge of their design and operational limits. Going further, the simulation also cycles the design through high and low voltage operation, worst-case corners for fabrication process, and the ugliest examples of jitter and timing you want to account for.
The result is a package that lets TriCN's designers know exactly how far and how an interface will go, and how much power it will draw. Depending on your application, and what your chip will be hooked up to, they can use the model to perform trade-offs for power, performance, reach, or noise immunity that will assure you the core will function under the worst-case conditions of your choosing.
While my analog skills are not what I'd like them to be, there were some details of the design, modeling, and verification processes TriCN uses that I did not fully understand. But from all I was able to get, I am ready to believe Ron Nikel, TriCN's CEO and CTO, when he told me that this approach produces much better results than using generic cores based on generic load parameters. And the other cool part is that since this is a semi-custom core, designed to interface directly to the rest of your design, you should be able to spend a whole lot less time integrating, verifying and debugging it. Besides saving time and money, TriCN's I/O-ware should let you concentrate your efforts where they should be put - on the value-added elements of your design.
While not terribly helpful, a little more information on the SPI-4.2 interface can be found on TriCN's website.
|