Delayed, But Not Deterred: The "Equalize
This!" Gigabit Backplane Challenge Forges Ahead
by Lee H. Goldberg
It all seemed so simple when I started the "Equalize This!" project -- I'd just invite a few leading SerDes manufacturers to run their latest chips on a state-of-the-art test bed at a leading university, collect the data, and publish it for the readers at i/oZONE some time in September. Unfortunately, my naïve hope for a speedy conclusion was the result of having spent too much time at the keyboard and not enough at the lab bench in the last couple of years. It seems I'd completely forgotten about how unexpected problems spring up around any real-world project with all the vigor of the crabgrass in a freshly-fertilized lawn.
The bad news is that thanks to obscure technical issues, summer doldrums, and industry paranoia, the project I'd hoped to complete by late September is now stretching out to sometime in mid-November.
The great news is that, despite the delays, "Equalize This!" test plan is finally moving along rather nicely -- and beginning to yield some interesting results.
A Rocky Start
The actual testing finally kicked off in early September, a bit over a month later than we'd expected. Most of the schedule stretch came from the fact that many of the companies I talked to were very nervous about doing something as unheard-of as publishing their performance data side-to-side with the competition. Apparently, what is considered commonplace in Consumer Reports and PC World is a radical and scary concept for chip makers.
Fortunately, spending a decade in the trenches writing about most major electronics manufacturers has earned me some level of trust with them. Although it took more time than I'd reckoned, I got a few of them to believe that my team could really structure a series of tests that would generate useful information without turning the event into a mud-slinging slug-fest.
To put everyone's fears to rest, we added several clauses to the rules governing the event. First, we promised to post the test results with some analysis but no ranking order. Besides preventing competing companies from using the results as a blunt marketing weapon, avoiding ranking parts by any kind of "goodness" makes sense because applications vary so widely that no single set of criteria would be anywhere close to valid.
We also agreed to follow the participation model used by the University of New Hampshire that allows participants to quietly withdraw from the tests if they don't like the test results they get. Besides saving face for a company that was gracious enough to work with us, it also gives them the opportunity to go back to the drawing board to see if there is anything they can correct in their chip or their test set-up to make things work better. Once we had these provisions in place, we were able to quickly sign up our first alpha-partners.
The Brave Participants
As of this writing, the official participant roster includes Accelerant, Quellan, and Vitesse. Their trust and support helped me gain the interest of at least three more major semi-makers who are currently in the final stages of signing on to our event, and a couple more companies who are strongly considering joining this first phase of testing. We'll post the names of these other companies in our soon-to-be-posted "Equalize This!" web page as soon as the paperwork is signed.
While somewhat short of the ten companies I'd hoped to have, the collection we've assembled should provide a reasonably-representative sampling of what the industry has to offer. From what I've seen so far, the data we generate from the chips will give us a much better understanding of how both binary and PAM-based SerDes technologies work under "near-real-world" conditions.
The Birth Of A Test Plan
Once we got the attention of a few companies, Dr. Sebastien Nuttinck -- our project's chief scientist at Georgia Tech -- was able to sit down with them and turn our baseline test plan into something that they felt would provide useful and unbiased results.
In some ways, the delays we faced have been a blessing, allowing us more time to make sure the tests we run produce the most useful information for our readers. While reviewing the plan with our early adopters, we discovered that manufacturers had concerns about what measurements we took that we had not anticipated.
We also discovered that some of the assumptions about the kinds of tests we could perform on the products were not quite accurate. Part of this was due to the fact that some chips were stand-alone SerDes products, while other components included their SerDes transceivers as part of a switch fabric or other VLSI networking component. This greatly affected the types of signals we had access to, and the kinds of measurements that could be made across all representative products.
In the end, Sebastien was able to develop a basic "vanilla" version that outlines a series of tests we perform on each part. The plan is customized for each chip we test to add additional measurements where possible, but the common format of the baseline results will allow everyone to get "apples-to-apples" comparisons on whatever we test.
Besides firming up the test plan, we selected a collection of three backplane environments. Tyco and Teradyne both graciously loaned us test articles that they feel represent good state-of-the-art backplane design and manufacturing practices. In addition, we have a third fixture that approximates the electrical characteristics of older FR-4-based backplanes that use older connector styles and layout practices based around the XAUI short-haul interconnect standard.
Together, they should provide a good first-order look into how SerDes technologies interact with typical channel characteristics. To make sure we capture the most challenging conditions, Sebastien has done an S-parameter analysis of all the (available) traces on each backplane and selected the worst-performing signal pairs for his speed, jitter, and cross-talk immunity tests.
Testing Begins In Earnest
Accelerant and Vitesse have already run their chips on our test bed and are so pleased with the experience that they are coming back to get a little more data. We'll post the results of both sets of tests as soon as we can -- possibly some time in the next two or three weeks. Quellan's chips are due back from the fab shortly, and we've been promised a first look at them around the end of the month. You'll get the data about the same time they are ready to release the normal details of their product to the public.
I have great hopes that we'll be signing up at least two of the remaining companies within the next week or so, and scheduling their chips for testing shortly thereafter. With a bit of luck, we'll be posting the final results of this adventure some time in mid-November.
Between now and the time we post the final results, I'll keep you up-to-date about any interim developments. Whether it's new test results, or the names of our mysterious new participants, you'll find the latest scoop here at i/oZONE.
As always, I'll be here to receive your comments, questions, or ideas for improving our little Gigabit bake-off. You can always reach me at: lgoldberg@green-electronics.com.