Deeds, Not Words: Moving From Harangue To Hardware
With The Equalize This! Gigabit Backplane Challenge
In a cooperative effort between Georgia Tech and analogZONE, we're running
a series of tests on commercial serial backplane silicon in an attempt to
shed light on many technical issues facing the high-performance SerDes industry.
by Lee H. Goldberg
It's been lots of fun to watch interest in high-speed SerDes gather momentum over the year or so I've been publishing i/oZONE. When I first hung out my shingle here, multi-Gigabit serial backplanes and interconnects were a relatively esoteric technology, reserved for products running at the far end of the performance spectrum. Now, thanks to the efforts of folks like Accelerant, Broadcom, LSI Logic, Marvell, PMC, and Velio, the price, power, and hassle factor of designing with 2.5-Gbit/s SerDes transceivers has fallen steeply.
But many issues still remain -- even at the now-common 2.5/3.125-Gbit/s speed level. What, for example, is the most effective equalization scheme for FR4-based backplanes, and are there times it is counterproductive? Are there more effective technologies for squeezing more bandwidth out of so-called "heritage" backplanes, found in older equipment? Is there any disadvantage to using some of the more efficient alternatives to the 8B/10B line coding scheme uses by most binary SerDes?
And what about the PAM/Binary debate? With several manufacturers offering their own 5-Gbit/s PAM-based products, and Agere adopting Accelerant's technology, PAM SerDes has moved from fringe to mainstream. Debates still rage over the best way to equalize a channel so that a complex PAM signal can be detected. Meanwhile there are still many open questions about where PAM offers a clear cost, power, or performance advantage over "traditional" binary products.
Then, just as I think I've got my head around these issues, there are other 5- and 10-Gbit/s SerDes technologies, which loom on the horizon, with their own issues. The mind boggles as theorists argue over the relative merits of their pet line-coding and equalizations schemes…
One of the ways I cut through the confusion was the "Great Gigabit Backplane Shootout", a moderated debate that was held on analogZONE late last year. The lively interchange between a dozen manufacturers covered most of these issues in a fair amount of detail and, if nothing else, helped identify the challenges that will define the next generation of SerDes products. The only frustrating thing has been that in the end, the debate was simply a collection of words, with no way to objectively extract the truth from often-conflicting claims.
This has changed recently when I was invited to help organize an event at Georgia Tech that put all these claims to the test. That's right, I'm in the process setting up a series real-life hardware benchmark characterization tests that will be run on a $1.5 million test bed facility located in Georgia Tech's new Atlanta-based industry research facility.
Because so much of the "rocket science" and "secret sauce" in the faster (5-Gbit/s and up) SerDes products is related to their channel modeling and equalization techniques, we've named our event the "Equalize This! Gigabit Backplane Challenge."
The Challenge is going to be run much like an old-fashioned drag race. The i/oZONE has invited all the major SerDes silicon makers to bring some of their production silicon to run on our "test track" where everyone will run under the same conditions. There will be at least three "classes" of chips, one for the 2.5-/3.125-Gbit/s transceivers, another for the 5-to-6-Gbit/s products, and an "unlimited" class for products running at 10-Gbit/s and up.
We've lined up a couple of PhDs and a bunch of test equipment, and are in the final stages of developing a test plan that will run a SerDes transceiver through a wide spectrum of tests to determine performance, noise immunity, jitter margins, and other critical parameters. We'll be running each chip over various distances across three flavors of industry-standard backplanes, to provide a sampling of the kinds of environments these chips will find out in the field. Once all the data has been collected we'll be publishing it here, for your enlightenment.
The project has taken shape very quickly after it was first conceived over a few beers at Supercomm in May. We have all the test equipment in place, and a first draft of the test plan is being circulated to our participants. So far at least half of the invitees have accepted our gracious invitation, and I expect that in a week or two, we'll see the rest of the pack signed on. Once we have a full list of players, it will be posted here.
With luck testing should begin by August 1, 2003 and we hope to have run everyone's chips on the test bed by the end of September. Of course this is the first time we've run such an event, so your mileage may vary. You'll see test results, and some analysis posted up here within a week or two of the end of the tests. In the meanwhile I'll keep you posted with updates on any interesting developments as they occur.
Of course, if you have any comments, questions, or burning insights about testing Gigabit Serdes transceivers, I'll be here, awaiting your e-mail at: lgoldberg@green-electronics.com.