That Big Sucking Sound
Can the new Interlaken specification for multi-Gigabit chip-to-chip
interconnects keep network equipment designers ahead of the bandwidth demand
curve?
by Lee H. Goldberg
An engineer's job is a thankless one, especially if you're involved with communications or networking. It seems like however much bandwidth you built into last year's box is not enough this year and you have to dive deeper into your bag of tricks just to keep even with the big sucking sounds you hear on the other end of your boxes' wires and fibers. That's why the recent joint announcement from Cisco and Cortina of the Interlaken open chip-to-chip interconnect protocol caught my attention.
From what I was able to learn about the technology behind Interlaken, in a recent briefing with Cortina, it looks like they have struck a good balance between performance and practicality, and have given this open specification enough flexibility to serve a variety of applications. If it can really deliver the goods it holds significant promise to give designers the bandwidth they'll soon need to support, and move past the 10-Gbit/s interconnect speeds being used inside today's most bandwidth-hungry boxes.
The basic concept behind Interlaken is a SerDes-based interconnect protocol that uses an enhanced SPI 4.2-like control layer to manage one or more high-speed serial channels. Each SerDes channel in an Interlaken interface can support speeds of up to 6.25 Gbit/s worth of raw bandwidth. And, thanks to its 64B/67B encoding scheme, much less of its capacity is lost to overhead than a comparable XAUI interface or other common SerDes standards that use 8B/10B coding -- even with an extra bit that allows control of dc balance. Incoming data packets are divided into smaller bursts, delineated by a burst header. These packets can be distributed across multiple channels as necessary to support low-latency data links with capacities of 100 Gbit/s or more.
Interlaken's protocol control structure handles the actual channel aggregation, allowing it to work with any number of lanes, and enables its bandwidth to scale linearly with each additional lane. Designers used to working with SPI interfaces will feel right at home since the individual serial channels are layered on top of a base packet interface that preserves the SPI4.2 burst and packet control conventions. Of course several additional mechanisms have been added to help keep the data flowing through the multiple SerDes channels in the proper order, including a regular meta frame that guarantees lane alignment and clock compensation.
Technical matters aside, the fact that Interlaken's technology is being provided royalty-free to the industry by Cortina and Cisco is a big plus. Of course, it still remains to be seen if the two companies are really as altruistic as they claim to be or if there are some sort of Trojan Horse, or other agenda embedded within the specification, that would put other companies at a technical or legal disadvantage. From what I've seen, this is really a clean specification, that's actually been designed with the overall welfare of the industry in mind, but I've seen too many marketing wars fought through specifications like this to completely put my fears aside until a few independent parties from the silicon and equipment communities weigh in with their opinions.
Then too, Interlaken will face some significant marketing hurdles in gaining widespread acceptance since it did not come up through official channels like the IEEE, ITU, or other sanctioned technical group. But, given the fact that I have not seen a similar specification in development with any of the usual suspects, coupled with the fact that it has the endorsement of Cisco, one of the largest consumers of networking silicon on the planet, it stands a better-than-even chance of gaining the momentum it needs to take its place next to the pantheon of other standards, protocols, and interconnect specifications that we use to stitch together our designs.
If it's widely adopted, and is really the agenda-free interconnect technology it claims to be, Interlaken could help accelerate the development of a healthy ecosystem of interoperable fractional-Terabyte silicon products. These in turn could greatly reduce the development costs and time to market for the next generation or two of communications and networking equipment.
Comments? Questions? New interface or connectivity specifications I should know about? Write me at: lgoldberg@green-electronics.com
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