Herding Cats, Nailing Jell-O
by Lee H. Goldberg
Whatever the DesignCon conference lacks in glamour, scantily-clad booth attendants, and the lavish parties found at larger, fluffier tech shows, it makes up with some of the best hard-core design-oriented content you'll find anywhere. The heavy-duty sessions covering the subtleties of both chip and board design are what usually pull me back to Santa Clara each spring but, this year, there were several equally interesting developments on the show's modest exhibit floor. While the significant increase over last year's attendance was big enough news, it was overshadowed by the large number of exhibitors demonstrating hardware that supported the OIF's (Optical Internetworking Forum) recently-approved CEI (common electrical interface) specification. The demonstrations, which were held at nearly a dozen booths only two months after CEI's ratification, were a clear indication that the confusion that's slowed the commercialization of 5 - 10 Gbit/s interconnects for the past year or two is passing.
The explosion of working
hardware was amazing. There were somewhere near a dozen backplane solutions
using various combinations of silicon, connectors, and backplane technology.
I even saw transceivers from Xilinx and Vitesse cheerfully exchanging data at 6 Gbit/s over a commercially-available
backplane.
Until now, the industry lacked a firm definition of either what was needed
from the transceiver, or an industry-wide agreement on the minimum channel
characteristics of the signal path. The already-difficult task of shoving
bits along less-than-ideal PCB traces at 5 - 10 Gbit/s was further complicated
by the political intrigues surrounding the subtle, and not-so-subtle, interactions
that occur between 
chips, connectors,
and the PCBs themselves at these rarified speeds.
Without a clearly-defined standard that gave chip designers a clue about the environment they were expected to work in, it was easier to herd cats than to get the industry to adopt a unified technology that would let it move beyond the current 2.5/3.125 Gbit/s backplane speeds. Likewise board and connector manufacturers struggled for close to two years to define their products with little or no guidance about which SerDes technology would ultimately be driving them. All this confusion made designing a 10-Gbit/s system a bit like nailing Jell-O to a wall.
Happily, the OIF stepped in with a big Jell-O hammer in the form of the CEI. Because of the extremely deep interaction between electronics and the backplanes at these speeds, the Forum decided to use an unorthodox approach that used co-dependent simulations to define the roles and responsibilities of each element in the system. The approach, which has been dubbed "StatEye," divides responsibilities between the systems' active and passive elements by using S-parameters to define channel response for a minimally-compliant backplane that a manufacturer's transceiver would be expected to drive and produce a minimum predicted eye opening. Similarly, backplane manufacturers must have products whose specs deliver an equivalent data eye when simulated using a hypothetical minimum standard transceiver and a 5-tap DFE reference receiver.
A passage from the OIF white paper "Interoperability Testing of the CEI" sums it up quite nicely:
The OIF took a radical departure from the channel compliancy methodology used by previous specifications. The OIF chose to use a statistical analysis methodology which considers all aspects of the system synergistically, based on a simulated transmitter and receiver. This provides a quantitative prediction of the post-receive equalization of the eye-opening for the channel's target BER performance. Channel compliancy for guaranteed interoperability is then based on having sufficient eye-opening for the stated BER. It is important to note that the simulated transmitter and receiver represent the minimum requirements of the specification, but do not define the actual algorithm that a silicon vendor is required to implement. Instead, the silicon vendor must develop a solution that will provide equivalent or better performance than the simulated minimally-compliant transmitter and receiver for any channel.
The CEI spec has been defined for short (chip-to-chip in a PCB up to
200 mm) and long-haul links (backplane, up to 1 m") operating at 6
Gbit/s, and for short-haul links at 11 Gbit/s.
Much like what open-source code does for software, the OIF CEI specs frees designers from being forced to be dependent on a single vendor for critical functions. Manufacturers will also benefit from having these clearly-defined functional specifications that have been structured to allow them enough room to differentiate their products through both cost and performance. And since only the minimum performance specifications have been set, manufacturers are free to use whatever "secret sauce" they want to deliver products which offer better performance, lower, power or cost, or any combination thereof.
Of course no solution is perfect, and there is already some talk among the more knowledgeable OIF members of the need for an informative budget (for 4-port S-parameter Sdd21) parameters that includes things like dielectric and losses, skin effects that would give better guidance in product development. I also worry that the CEI pretty much leaves it up to the manufacturer to add its own margins in for process variations and aging, but in whole, the new specifications seem to have broken loose a whole bunch of energy that's going to power the development of solutions for the ATCA backplane and other critical markets.
Comments? Questions? Your observations regarding DesignCon? Write me
at lgoldberg@green-electronics.com.