The Great Gigabit Backplane Shootout - Question
#9
The high fT transistors typically needed in a Receive equalizer are usually unavailable in the plain CMOS technologies most suitable for ASIC integration.
SERDES are typically smaller and less complex which allows for higher levels of integration.
The use of PAM increases the amount of silicon dedicated to analog circuitry, which is neither dense nor power efficient. SERDES functions tend to use smaller area of analog circuitry, so would be denser while consuming less power. A large ASIC would need to dedicate less space and power to a SERDES solution.
As item 8, receive equalization is better compared to transmit pre-emphasis due to lower crosstalk.
The most commonly used bandwidth compensation scheme used in AISCs is pre-emphasis. Simple first order analog equalizers are good candidates for bi-level SerDes and DSP based equalizers are good candidates for PAM channels.
It is not clear that equalization is an issue unless the technology chosen results in a much larger or higher power implementation. Most of the ASIC processes today have mixed-signal options so the suitability for an ASIC is derived from the need to keep the power and core size minimal. A DSP solution which includes an FEC will be very large and will draw significantly more power than alternative solutions making it too large for practical use in ASICs. When full duplex 4-PAM is implemented using an analog architecture, its size is roughly equivalent to a 6.25G two level solution with DFE but is lower in power. Both solutions will have to come in below the XAUI power bar of 400mW per 5Gb/s (800 mW per 10Gb/s) to be competitive however two level signaling may not meet the performance needs of the general market.
Another critical consideration is substrate and other noise coupling both from and to the transceiver core in ASIC applications. These issues become increasingly difficult to handle as the clock rates increase. Published research work carried out by companies like Intel has shown that techniques such as deep n-well isolation are less and less effective as the speeds climb into the multi-GHz range. Clearly the 4-PAM full duplex architecture offers a significant advantage to an ASIC implementation due to its operation at 1.5GHz compared to the 6.25GHz of the two level solution.
SERDES with pre-emphasis are the best choice for ASICs with a large number of channels due to the following reasons:
Analog equalization is superior it is faster and consumes less power compared to its digital counterpart. However, analog equalization requires a great deal of analog experience to implement.
Fixed programmable linear equalization is most suitable in this situation due to simplicity and performance.
NRZ. When port count goes from 64 to 128 ports, then die size and power are king. Tx pre-emphasis is almost free, and simple, fixed pole Rx Eq is also very power and area efficient.