The Great Gigabit Backplane Shootout - Question #7

Accelerant Says…

Yes, in average to worst-case backplane traces, at data rates of 2.5Gb/s and up, PAM4 is clearly superior. At low speeds, or for short traces (chip-chip), either system works well, so the simplest is the most practical.

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Agere Says…

PAM coding does not perform well in high crosstalk environments. This is a serious limitation since some 6Gbps serdes are being targeted to run on 3Gbps backplanes.

NRZ is easier to develop and less susceptible to crosstalk, but requires higher bandwidth and potentially higher cost in equalization at the higher speeds.

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BitBlitz Says…

Where channels are very good, as is expected of some of the new 10GB/s backplane proposals, there is no particular advantage to multi-level coding. Where channels are very bad, as exist in some legacy backplanes, there may be no choice but to go to multi-level coding as the binary signaling solutions just don't have the dynamic range to equalize the channel.

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Broadcom Says…

In new backplanes where the designers can select the best backplane material, connectors, and design the backplane to minimize cross talk, bi-level SerDes is clearly a better choice to achieve higher data rates.

A PAM encoded approach can be used to upgrade existing designs to faster speeds than originally designed for. For example, a backplane designed to operate at 622Mbps may be able to support 1.25Gbps or higher with specially designed PAM encoded SerDes devices.

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KeyEye Says…

For any given communications channel once the system limitations are understood, there is an optimal solution. These types of chassis are limited in large part by the connector performance. However, the connectors are thoroughly analyzed and this data is available to the public. One can calculate the Shannon capacity for this copper backplane channel given the appropriate data. The Fig. shows that even without using a FEC a good deal of bandwidth is still available.

The best solution is one that uses the bandwidth the most efficiently. XAUI transmits 10Gb/s using 8 signal pairs, thus achieving 1.25Gb/s per pair full duplex while using close to 1.6 GHz of bandwidth. While HSBI and EchoWave both effectively achieve 2.5 Gb/s per pair, EchoWave is able to do this while using only 781 MHz because of its full duplex 4PAM architecture. HSBI transmits in a two level simplex fashion and uses close to 3.125 GHz of bandwidth.

Several companies have explored the possibility of using full duplex, multi-level techniques in the past to maintain lower signaling rates. However, they did not have the benefit of many man-years of exposure to echo cancellation design techniques and were forced to explore alternate solutions to these problems. As recently as 2001, research work being done at universities including Stanford explored these approaches but noted problems with receiver signal leakage from full duplex replica transmitters and additional NEXT sensitivities that negated this approach. Not many people will argue that keeping edge rates and signal energy down leads to better system performance. The key is adopting an architecture that avoids many of the common pitfalls that come with doing this. When architected and implemented correctly this approach yields a transceiver with superior performance across the widest possible application space.

In the past, virtually all high-speed, band limited copper communications standards have gone through this evolution. One can look to Gigabit Ethernet, ISDN, HDSL, and T1/E1 as examples. These markets were initially serviced by simplex transceivers early in the market's history, only to move to full duplex solutions as the data needs increased. The backplane market today does not look much different than the Ethernet market looked like four or five years ago. To go from 100 Mb/s to 1 Gb/s using Category 5 copper cabling required a transition to full duplex technology. Although, some of the impediments that have to be addressed are different in the backplane, the underlying nature of the channel will also require a move to a full duplex architecture.

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Marvell Says…

Most applications are better served by binary signaling. Some very specific cases may be better suited for multi-level signaling.

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Mindspeed Says…

MLS chip design is still difficult to implement. There will be even less data eye margin for MLS with the decrease of supply voltage for deep submicron CMOS at 5-10Gbps. In addition, threshold variation, process corner variation will pose a challenge to achieve good yield and robust performance.

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National Says…

• The applications legacy compatibility requirements, the channel's transmission line characteristics, and the required serial data rate determine whether binary or multi-level coding is the optimum technology.
• In general, binary coding is best up to 6.25 Gbps, and multi-level coding shows great promise for serial data rates greater than 6.25 Gbps.
• At data rates less than 2.5 Gbps and depending on the channel characteristics, the binary level transceivers may require TX and RX EQ to recover the signal.
• From 2.5 Gbps to 6.25 Gbps, serial data transfers will require TX and RX EQ, and the channel characteristics determine the EQ techniques and strength.
• At data rates above 6.25 Gbps, binary coding becomes more difficult due to channel loss and multi-level coding may prove to be the best option for transferring data across a copper backplane. However, at these data rates both technologies will need to rely on some combination of expensive surface mount connectors, exotic backplane materials, and manufacturing techniques (such as blind via, back-drill via, micro-via, etc.) to minimize impairments.

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PMC-Sierra Says…

No response received.

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Velio Says…

PAM may be appropriate for old, 1G backplanes where the backplane is really bad and needs to run 4x or 8x what it was originally designed for. It may also good for situations where artifacts of 1st generation designs have really bad crosstalk. Otherwise it is not indicated. See our PAM vs. NRZ white paper.

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