The Great Gigabit Backplane Shootout - Question
#6
While Shannon's limit is hard to apply to a channel dominated by non-Gaussian and signal-dependent noise (crosstalk), it clearly points in the right direction: the limit depends upon the channel and its noise characteristics. Higher speeds (10Gb/s) combined with normal worst-case trace lengths demands better material properties (dielectric loss) and better connectors (less crosstalk).
Performance is limited by the transmission media. Practical capacity limits are unknown at this point.
Traditional SerDes architecture has its own serious limitation. There are two widely popular design approaches that exist today - The Analog & The Digital Over-sampling.
The Analog design has a limit on number of channels on a given die. On the other hand, digital over-sampling architecture is limited by the inherent speed of the process technology.
However, a 10G backplane require many monolithic devices that integrate multiple 10G channels. In order to achieve that, a new architecture must be deviced. BitBlitz has patented solutions to integrate multiple channels at 10Gbps and beyond.
Typically, PAM-4 is implemented in primarily digital circuit. As such, there is an upper frequency limit of operations, as dictated by the process. For example, 0.18um CMOS has an Ft of 30GHz - which means the device cannot operate at speed above 3Gbps. This severely limits the options available to the digital signal processing approach, and what options are available dissipate more power.
Depending on the backplane, the performance limitation for the 2-level SerDes (NRZ) can be any of the line impairments mentioned above (see Question 5.) The PAM approach should generally achieve better performance at the cost of higher complexity and higher power which could ultimately limit its applicability.
Two level signaling has been the workhorse for several generations of semiconductor technology. As rise/fall times have gotten faster and bandwidth energies have increased, the technology is approaching the limits of the laws of physics. The SERDES being described today are full communication transceivers - the distinction being the amount of signal processing that must take place inside the device. As signal integrity engineers are realizing, even slightly improved materials such as GETEK or high Tg Nelco, which increase the BOM (bill of materials) cost, will only permit utilization of 6.25 Gb/s two level solutions in a small subset of the market. Going to high performance materials like those from Rogers Corporation and using higher performance connectors can double the bill of materials (BOM) cost.
By offering a path to 20 Gb/s on today's copper backplanes, full duplex, PAM-based solutions are extending the life of today's low cost backplanes by ten years, and allowing designers the freedom of focusing on how to best utilize the additional bandwidth.
Multi-level signaling has theoretical performance penalty for simply implementing the multiple levels. If the channel characteristics are such that the gain due to immunity to cross-talk, etc. offsets the penalty, multi-level signaling may be justified. In most cases, multi-levels are not optimum.
This question addresses a constellation of issues closely tied in to questions #5 & #6. We have answered these three questions in an extended form in Question #7. Please see the table in the answers to question #7 for a full explanation.
Binary coding is better when low cost, backwards compatibility and future integration of SERDES into larger devices is a necessity.
See our PAM vs. NRZ white paper.