First Fruits -- Accelerant and Vitesse Are First
To Deliver Test Data To The "Equalize This!" Challenge
by Lee H. Goldberg
The "Equalize This!" test team is pleased to present the first
data sets to emerge from the test
bed we assembled at Georgia Tech for our Gigabit Backplane Challenge.
Although convincing a half-dozen major SerDes manufacturers to have their
products evaluated was more challenging than giving a nervous cat a bath,
it looks like the effort was worth it. After several delays, it's a pleasure
to kick off the main part of our program with data collected from our first
two participants: Accelerant
and Vitesse.
The Equalize This! Gigabit Test Bed
About The Tests
Before you dash off to look at the data itself, it might be useful to understand a bit about the tests we're running and the data we're collecting. If you haven't done so before, please review the master test plan we developed, as well as the short explanation of the reasoning behind the tests that we posted in our original introduction to the event.
Data Sets Ready For Download
During the next month or so we'll also be collecting and publishing test data on products from Broadcom, Marvell, National Semiconductor, and Quellan, but for the moment we've got the first round of data collected on the Accelerant AN6425 and the Vitesse VSC3108. The data is available from our project's FTP site at
I've also spent a little time going over the data and have extracted a few observations that may be helpful to you in making sense of what you're looking at. For what they're worth, they're posted below.
Apples-to-Apples -- Mostly
Wherever possible we tried to faithfully replicate all tests and measurements on both chips we ran on the test bed to make "apples-to-apples" comparisons between devices and line coding schemes. As you'll see in the "Color Commentary" section, this was not always possible.
Due to differences in the chips' features, plus limitations of the evaluation boards and driver software, we were not always able to match each chip on a test-for-test basis in this initial shake-down run. Despite the gaps, there is already more than enough data here to be quite useful as a baseline for understanding many things about how silicon and circuits work. Nevertheless, we hope to bring both Vitesse and Accelerant back to help us "fill in the blanks" some time before this first series of tests is over.
As described in our test plan, we tested the chips in three test articles developed by manufacturers to simulate "typical" backplane environments.
Tyco supplied the "HmZd-XAUI" test article as an example of a "modern" backplane and its "HmZd-Legacy" board (See Fig. 2) to simulate a "legacy" environment, designed to less stringent specs.
Fig. 2: Tyco HmZd-Legacy Backplane
Teradyne loaned our project its GBX4 evaluation board (see Fig. 3) as a representative of its 5+ Gbit/s products.
Getting Aggressive
One of more the important tests we ran exploring the impact of near-end crosstalk (NEXT) noise from other channels on the overall performance of the SerDes link. This was accomplished by running a second SerDes signal, referred to as the "aggressor" channel, in an adjacent set of traces that was deliberately selected for their close coupling to the "victim" channel, i.e. the circuit under test.
This "worst case" channel was selected from the trace pairs that could be accessed on the test article using small-signal (S-parameter) measurements taken with a 4-Port VNA. The channels were selected based in a worst-case combination of transmission impairments and great cross-channel coupling. One interesting thing to note is that in each of the test articles we used, the worst-case traces end up being the ones that are very close to each other near the connector with poor ground shielding.
The bit sequence chosen for the aggressor was a PRB 2^23 -1 pattern, mostly because it offers a higher degree of randomness. This results in a better (wider) spectral distribution that the folks at GA Tech feel creates even more interference than an 8B/10B-encoded signal.
The multiplier you'll see in the header of each data set (0X, 1X, 2X, 3X) refers to the amplitude of the aggressor with respect to the signal in the "victim" channel for that particular set of tests. So why did we use interferers that were two and even three times bigger than the signal? In part this was a way to simulate the sorts of reinforcement effects you might see when a two worst-case x1 aggressors are completely in phase. It also seemed like a great way to both stress the circuits we were testing, and to get a bit better sense of the interactions between channels in extreme conditions.
The tests were run for each backplane and chip combination, using different bit sequences and aggressor amplitudes over signal paths ranging from 1 inch to 30 inches. Vitesse ran on six different lengths (6, 18, 24 & 30 inches on Teradyne, 1, 16 & 30 inches on Tyco) at 2.5 Gbit/s and 5 Gbit/s. Due to time constraints, the tests on the Accelerant chip were somewhat more limited in the number of lengths we were able to test. Details can be found in the chip-specific commentary below.
Look & Feel
When designing the tests our research team tried to provide both quantitative parameters and useful images. You'll see both measured parameters and the familiar "eye diagrams" because they felt that screen shots of the actual signals allows for a visual interpretation of data as well as blind crunching of raw data. Hopefully this will help give you a better intuitive feel for the actual data and how it compares between tests.
The Accelerant AN6425
The AN6425 we tested is a precursor to the recently-released AN6420 transceiver that was reviewed recently in i/oZONE. Both the AN6425 and the newer AN6420 have self-adaptive abilities, and the ability to handle PAM-4 encoded data at speeds up to 6.25 Gbit/s, but there are some differences. For one thing, the part we just tested only runs in PAM-4 mode while the newer AN6420 has fully-guaranteed binary NRZ and PAM modes over full speed range. Since the AN6425 is rated for operation only in the PAM-4 signaling mode, we will have to reserve the binary signaling data for the next round of tests when we can get our hands on the AN6420. There are a couple of other differences in their equalization capabilities, but the AN6425 that we were able to test this time provides a good idea of what the Accelerant parts are capable of delivering.
Because there is so much controversy about the merits of binary versus PAM signaling, our test team worked hard to create tests that enabled apples-to-apples comparison with binary parts.
Accelerant delivered a well-conceived and complete evaluation board to accompany the transceiver. Its well-designed user interface made most of the complex features supported by the chip (internal BERT) relatively easy to configure and operate. The only downside was that that very rich feature set that made the board complete also made it a bit more time-consuming to master initially.
The AN6425 transceiver chip was equally complex, with lots of adjustments and test modes available to us. In fact we actually relied on the chip's internal diagnostic circuits to our derive margin (bathtub) measurements. Margin was calculated this way because a traditional BERT test set up cannot test PAM signals. The center eye in the PAM constellation was used to measure jitter margin because it is the most difficult portion of the signal to recover properly and most susceptible to closure. And just to set the record straight, please remember that BER = BYTE Error Rate in PAM.
The AN6425 was tested on Tyco HMZD Xaui, HMZDLegacy, GBX and VHDM test fixtures at 3.125 and 6.25 Gbit/s (2.5G and 5G user data rate). Because the chip had to be configured each time to connect its internal sample channels to extract the signals for the eye diagrams the tests took much longer to run than anyone had expected. The limited time window Accelerant had allocated for testing forced our team to use only two channel lengths (the longest run available and the 1 inch channel) for each backplane for this series of tests. We are currently negotiating with Accelerant to return for a full set of tests on the newer AN6420 chip which will include all available channel lengths and exploration of binary mode operation.
In operation the transceiver was very robust, and did not fail. At the higher speeds and the more extreme crosstalk conditions we threw at it, you could see degradation in the eye diagram, but it did not kill the operation (see Fig.4a and Fig. 4b). Part of this is explained by the fact that the Accelerant architecture places an encoder (scrambler) ahead of the PAM encoding circuitry to guarantee energy balance in the signal. I think that this is one of the things that makes it very insensitive to bit sequence.
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Of course there is a price to pay for such performance, and in this case one of the big penalties is the 25% overhead in bit rate you pay with all that encoding. Also the transmitter's pre-emphasis adjustment requires feedback to keep it in tune with changing conditions. This can be accomplished either with an in-band back channel or via an external connection between the Tx and Rx elements -- either of which adds a level of additional complexity to a design. For the record, our tests employed an external connection to deliver feedback to the transmitter.
Just to avoid confusion when you read the Accelerant test results, please note that the references to "Binary" and "PAM-4" in the labels above the eye diagrams refers to the kind of signal we ran in an adjacent set of traces to form an interference-generating "aggressor" channel. While it's unlikely that you'd see a binary signal running on the same backplane as a PAM signal, we decided to see how heavily we could stress the victim channel by using both kinds of signals. As expected, the PAM signal's lower symbol rate presents much less crosstalk. Nevertheless, the device demonstrated good performance under most conditions in the presence of binary interference.
Data Sheet AN6420
Data
Sheet AN6425
The Vitesse VSC3108
Vitesse selected the recently-announced VSC3108, a 3.6 Gbit/s 40 x 40 crosspoint switch with integrated SerDes transceivers for our tests because it is a good representative of the highly-integrated devices that they equip with SerDes interfaces. Like most recent Vitesse parts the VSC3108 packs both a transmit pre-emphasis circuit and a receive equalizer. analogZONE reviewed the VSC3108 in the December 22, 2003 issue.
We found that Vitesse's simpler DIP-programmable evaluation board is very straightforward and easy to use for many basic functions. Unfortunately, limitations with the current evaluation board (and its software) made it difficult to set up and control some of the more advanced features, such as the on-chip receive equalizer. Consequently, this first series of tests was limited to exercising the pre-emphasis circuits on the transmit side with no equalization added. As with Accelerant, we are currently negotiating with Vitesse for a re-match using their next-gen evaluation board that will allow us to explore the chip's equalization capabilities.
Within the constraints imposed by the evaluation board, the VSC3108 did a great job for the most part -- although there were a few problems as described below.
We found that the VSC3108 worked quite well in "medium" performance environments (2.5 Gbit/s) using only transmit pre-emphasis, but had some issues at 5 Gbit/s speeds on longer traces (see Fig 5a and Fig . 5b). I suspect much of the problem is because the VSC3108 had no 8B/10B encoding to provide dc balance. This could easily explain most, or all, of the problems experienced at higher frequencies and longer lengths.
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While we did not have time to do it for this set of data points, 8B/10B encoding can easily be easily added to the link, something we hope to do when we re-test the part on the new computerized evaluation board Vitesse is making available shortly. We expect that this, plus enabling the VSC3108's receive equalization functions will significantly improve performance at higher speeds and longer runs.
We look forward to getting the chip back in the lab soon after Christmas to run it in all its modes and see how much receive equalization and 8B/10B encoding can be used to improve performance in challenging conditions.
Conclusions
Running this first pair of chips through the "Equalize This!" test bed was a big learning experience for both chip makers and researchers. Like most first-time events, there were the inevitable technical problems, logistic snags, and partial data sets to contend with. Nevertheless, there should be enough information here to help you begin to make sense of the many issues surrounding how high-performance SerDes works in the real world Vs. the manufacturer's data sheet.
In the following months we hope to add to the performance data we have
for the Accelerant and Vitesse parts, as well as bring you complete results
from several other manufacturers including Broadcom, Marvell, National Semiconductor,
and Quellan.
As always, I'm here to receive your comments, questions, and ideas for improving our little Gigabit bake-off. You can always reach me at: lgoldberg@green-electronics.com.
