The Great Gigabit Backplane Shootout - Question
#12
This situation is exactly where PAM signaling enjoys its strongest advantage; an existing backplane originally designed for a much lower speed, (using older, less efficient connectors), built in FR4 or similar material, and needing to move 2-8x the original data throughput. The large loss, reflection, and crosstalk impairments in this kind of channel produce a performance "wall" at a lower data rate for binary signaling. Our PAM solution has already been shown to work at 6.25Gb/s on channels built for frequencies as low as 622MHz.
If the existing system upgrade is realized by changing the line cards, but continuing to use the existing, low bandwidth backplane, then silicon vendors who can develop sophisticated equalization schemes inside their SERDES transceivers will be most successful. If the system upgrade includes higher capacity backplanes, the silicon vendor who can provide the smallest, lowest power, integratable solution will be most successful.
To target existing equipment, new device must support existing line card - meaning interoperability with existing transceivers. And to interoperate, both equalization and pre-emphasis must be implemented.
From a deployment perspective, legacy box has reached its power limits. For example, typical central office can supply 200W per square feet. Many legacy systems consume upwards of 500W per square feet. Not only do these systems draw more current than safely supplied, it may violate NEBS standards. As a result, power density is a critical consideration as one upgrade backplanes to even higher speed. SerDes, dissipating less power than PAM technology, tends to be favored in this context.
No answer supplied.
Legacy systems offer challenges in several areas. These systems have strict power requirements, utilize FR4 and first generation connectors. New SERDES are doubling the data being transmitted across the backplane. Along with signal losses and NEXT, the board designer faces the need to keep BER (Bit Error Rate) low while not increasing the overall system power.
A bit error rate of 10-12 is common for most SERDES and backplane transceivers on the market today and is being proposed as a minimum for several next generation transceivers. This is no better than last generation systems yet the backplane will now be handling up to 640 Gb/s - 4x the bandwidth of the previous generation box. Since any data error requires system software intervention, which in turn limits equipment performance, increasing data rates require much better levels of BER than before. BER levels of 10-15 to 10-17 are now being requested by system manufacturers.
Today's fast I/O solutions have set the power bar for 10Gbps at close to 800mW. This number is built into many system power budgets. In addition, higher speed ASICs elsewhere in the system are demanding increased power due to faster operating speeds and greater data handling. In order for the system designer to get closure on his power budget next generation transceivers cannot increase the equivalent power per 10Gb/s. This is critical to many telecom equipment makers since exceeding power dissipation budgets in a central office can require requalifying a whole system trunk. This is unrealistic in today's economic environment. Rather than modifying designs to accommodate the limitations of SERDES, equipment designers need low power, "plug and play" backplane transceivers. These transceivers must provide improved performance over the same material sets and connectors at much lower BER. Designers do not want to spend time tuning or adapting to the peculiarities of each SERDES. Any compromise in this formula prevents equipment OEM's from making use of the advantages gained by going to higher data densities in their equipment.
One other area that must not be overlooked
is spectral compatibility. This is an area that historically took a significant
amount of work to resolve during the various telecom and Ethernet standards
development processes of the past 10 years. Yet, it has gotten little consideration
in recent backplane SERDES discussions.
Many systems today are using XAUI cores or standalone XAUI devices. These devices were originally designed to drive 20" of FR4 for MAC (Media Access Controller) to optical SERDES applications. Clever design extended these links to 30-34" on FR4 but at 10-12 BER there is very little noise margin left. Today's proposals of running 6.25 Gb/s signaling rates in the same systems will degrade XAUI noise margins significantly to the point where legacy cards could fail in the field. While low pass filtering on XAUI receivers in some cases may solve this problem, nothing can be done for XAUI transceivers installed on linecards already in the field which will suffer from the crosstalk generated by their higher speed neighbors.
Depends on the channel characteristics of each equipment. Some older systems have a lot of cross-talk, whereas others are designed very well. Most of the cases are addressed by regular SERDES with pre-emphasis. Some extreme cases require special signal processing.
One of the major challenges is that legacy backplanes were originally designed for 1Gbps data rates or lower. Attempts to increase the throughput to 2.5Gbps and 3.125Gbps have been successful, achieving 10e-15 BER. However, to run at 5Gbps, the cross-talk and eye opening at the receiver are at maximum and minimum acceptable levels, making the data recovery, in some cases impossible even with equalization. It is required that either the transmitter includes pre-emphasis and/or the backplane is upgraded. We believe that BLS is suited for systems that require 622Mbps to 5Gbps, while the MLS is suited for systems that require 5Gbps to 10Gbps running across backplanes not fully optimized for these data rates.
Binary signaling is the best fit for upgrading existing equipment. Those systems have backplanes designed for binary level signaling that will perform best with binary level transceiver upgrades.
Connectors seem to be the biggest problems. Many legacy connectors have crosstalk issues where they are not impedance controlled or not designed for high-frequency operation.
If properly modeled, binary coding is still most efficient. MLC may make sense in certain acute situations where a backplane or connector is that bad, however, most successful platforms (where there is an installed base) are usually designed relatively well.
NRZ is generally best except in worst case conditions, as defined in our separate PAM vs. NRZ white paper.