The Third Time's A Charm! -- National Semiconductor's
SCAN50C400 SerDes Meets The "Equalize This!" Gigabit Backplane
Challenge
by Lee H. Goldberg
The "Equalize This!" test team is pleased to announce that the test results of National Semiconductor's SCAN50C400 quad SerDes transceiver are now available for download along with the data from our other participants at http://hal.yamacraw.gatech.edu/eqthischal/public_download.html. With National's transceiver (reviewed) now having completed the gauntlet of tests on our Gigabit Backplane test bed, we've now got half of our original participants' data posted on the site. With experience from the partial data sets collected from the Vitesse and Accelerant chips, National's test run went rather smoothly -- at least from an operational standpoint.
Our Evolving Tests
As with any first-time venture we've learned lots along the away. Perhaps the most important lesson we've taken from the test runs is how to present the data we've gathered in the most useful manner for readers trying to make sense of the confusing, and often conflicting claims made by the manufacturers. Producing data that enables meaningful "apples-to-apples" comparisons between products was a significant challenge here, mostly because of the wide variety of parts we're trying to test. Although we are still following our original goal of looking at how different equalization, pre-emphasis, and line-coding techniques can be used to improve the throughput of a serial backplane channel, we've had to make accommodations for the fact that the SerDes silicon we work with comes in many different forms.
This involved developing some sort of metrics that could be applied to chips that might not have identical collections of functional blocks (CDR, equalization, etc). Sometimes we were able to work around this by running the chip in conjunction with a second chip (as in the case of National), or using the equipment in the test bed to make up for a missing element. The other challenge is that not all the products we test give us access to the same parts of the signal chain. As you will see, we were able to address some of these differences with some additions to the procedures we use to collect and present the data.
We also ran into some other issues that we're still working on resolving (see More Apples-To Apples Issues below.)
Our Updated Data Format
With first test runs behind us, we've fine-tuned the test reporting format a bit in the hope of making interpretation of the results as well as side-by-side comparison as easy as possible. Perhaps the most significant change came when we came to understand that not all devices we test provide us with access to the receiver signals before they enter the CDR block.
We have been using the pre-CDR receiver signals and bit error rate (BER)
measurements to generate "bathtub plots" as a common metric of
"goodness" that we can easily extract from the wide range of chip
architectures we test. The problem is that in the case of the SCAN50C400
(and several other parts we'll be testing shortly), we do not have direct
access to the receiver output ahead of the CDR circuit. Since the post-CDR
signal will produce a "clean" plot until the receiver lost lock,
it would be meaningless. In cases like this it seemed reasonable, then,
to define a pass/fail threshold as the combination of speed, channel length,
and adjacent (aggressor) channel noise that allow the channel under test
to achieve a minimum BER. We will then use these pass/fail results to create
a set of tables that allow the reader to quickly interpret the results.
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| Channel | ||||
| 6 inches | Passed | Passed | Passed | Passed |
| 18 inches | Passed | Passed | Passed | Passed |
| 24 inches | Passed | Passed | Passed | Failed |
| 30 inches | Passed | Passed | Passed | Failed |
Of course, we will also continue providing you with bathtub plots and eye diagrams wherever the chip and its evaluation board up permit access to the pre-CDR receive signal. Finally, please also note that in the case of parts like the Vitesse VSC3108 which do not have an on-chip CDR function, we will be unable to produce a pass/fail table, and we'll only publish eye diagrams and bathtub plots.
Setting The Pass/Fail Threshold
For the purposes of our tests, we chose the BER pass/fail threshold at 10E-11. This threshold level was chosen in part because there was a rough consensus in the lab that this was the maximum acceptable level of errors that a carrier-grade data link could tolerate for extended operation. We also decided against using any lower BER thresholds because unless we used some statistical hand-waving on a smaller data sample, it would dramatically increase test durations -- and nobody wanted to wait until the next Ice Age to see the final results.
Testing The SCAN50C400
As my earlier review indicates, the SCAN50C400 is a relatively straightforward SerDes device, which has some de-emphasis circuitry and other signal-conditioning features but still relies fairly heavily on an external equalizer (or other signal processor) circuit to handle channel compensation in more challenging conditions. In this case, the test board used the Maxim MAX3784.
The SCAN50C400 is engineered to be a solid, relatively-simple device, with sensible trade-offs between price and extreme performance. We saw pretty "normal" performance overall, in terms of sensitivity and clock stability. It performed very well at 2.5 Gbit/s and also at 5-Gbit/s. It displayed problems only where forced to operate over particularly difficult trace runs and more daunting levels of aggressor channel interference.
Results Highlight Backplane/Silicon Interactions
Interestingly, the "vanilla" test results this part delivered gives us an excellent opportunity to examine the characteristics of the backplanes we're using for our tests. Without the extreme channel compensation offered by the Accelerant device you start to get a better sense about how heavily backplane characteristics interact with the silicon. The test data clearly shows how some designs allow the same SerDes chip to work at much longer trace lengths, and under much higher levels of adjacent-channel interference.
While time and resource limits prevented this first phase of testing from going as deeply into silicon/backplane interactions as I'd like, these insightful glimpses we're getting should at least provide some useful reference points when you look at SerDes manufacturers' performance claims. I'm very grateful to the folks at Teradyne and Tyco for being brave (and generous) enough to loan us environments that at least begin to reflect some "real-world" conditions, even if their top-line products perform much better these days. It is a big help to those of us trying to design with multi-Gigabit SerDes products, especially in retrofit applications.
After we'd collected the data, National did a conscientious job of reviewing the results, and expressed a few concerns about whether our test methodology produced "apples-to-apples" results between the chips we run on the test bed. They rightly point out several differences between the test set-ups we used to collect the data on the different chips, and that this makes a direct comparison between the first two chips in our test series (especially the Vitesse part) difficult. National's analysis of our test methodologies (which we've included below, National Says) will help you understand some of the challenges we face in testing such a wide cross-section of SerDes technologies.
Despite these caveats, National seems to agree with us that there is enough useful information and has released their test data for public review.
Of course there are always two sides to a story and we've addressed many of National's concerns in a follow-up analysis that follows their remarks, analogZONE Says. While many of National's concerns do not appear to affect the accuracy or validity of our test data, some of the points thy have raised have helped us to better understand and improve our test procedures. We are grateful to National for their insights. They have ensured all subsequent tests in this series produce data that will make direct comparisons between parts much easier -- in spite of architectural differences that inevitably arise.
Our experience with National will also help shape the second phase of our tests. Hopefully this, and subsequent exchanges, will also help you get the most out of the data we've produced here.
National Semiconductor Says…
We are proud to be a part of the "Equalize This!" Gigabit Backplane Challenge. It is a great opportunity for system designers facing the challenge of multi-gigabit data transfers to see data collected and reported by an unbiased test lab. This testing allows the designer to examine multi-gigabit chip performance in real backplanes. This is exactly the information that National Semiconductor wants to provide to our customers.
When you examine the test results, National Semiconductor recommends that you look closely at the Measurement Setup diagrams on page 5 of each report. Even though the goal is an "apples-to-apples" comparison, this is difficult when the chip functions and backplane adapter boards are different. Try as they may, these diagrams do not clearly explain the different electrical paths and circuits being tested by the BERT in each case. It is important for interpreting the test results to clearly understand the circuits involved in each of the tests.
The attached diagrams show our understanding of electrical circuits in
each of the tests. In the Vitesse and Accelerant tests, it is our best guess
from the information available.
Figs. 1 and 4 detail this path for the SCAN50C400. The National Semiconductor chip test covers every channel of the Quad channel by passing through the on-chip CDR four times. National recommended this test to show the chip working on all channels at the same time, which closely mimics a real world application. This is crucial when comparing the SCAN50C400 to the Accelerant and Vitesse test environments. Both of those tests are a better case because only a single channel of the quad device is in operation. By working only a single channel, there is less likelihood that the jitter from adjacent channels is going to interfere with the BER.
It is also important to see the difference in the chip functions and testing. For example, the Vitesse VSC3108 does not include a CDR or mux-demux function on chip. Also, it is clear that the Accelerant set-up does not perform an independent BERT on the data, or whether there is BERT being performed on 5 Gbit/s worth of data. However, it is not clear whether the Accelerant chip has any CDR in the test data path or if the demux function is in the test data path.
In conclusion, National Semiconductor is pleased to be able to share independent test data with all analogZONE readers. We would also like the readers to have all the information they need to correctly interpret the test results. Therefore, we suggest that there be an open forum for Q&A on the test conditions and results to further everyone's understanding of the Equalize This! testing.
analogZONE Says…
National is correct in pointing out that there are differences in the test set ups we use for the various chips we are running in our lab. By and large, this is done to accommodate the different interfaces presented by the manufacturers' evaluation boards, and the different levels of functionality of each chip.
In National's case, their chip's back end is a 4-bit LVDS interface (Data Sheet) which did not hook directly up to the BERT equipment in the lab. We solved this by using one of the channel's serial CML inputs to bypass the LVDS interface and feed it to the transmitter via the chip's high-speed loop-back (HSLB) path.
A similar scheme was used on the receive side to provide a serial output for the BERT to measure. Within the constraints of the physical differences of the evaluation boards, our test team strove to minimize the differences in the electrical characteristics of the interface between the board and our test bed. This included using the same length and brand of premium-grade SMA co-ax cables for each test run. To the best of our knowledge, we were able to implement hook-ups that did not appreciably alter the jitter response or other critical parameters of the IC under test. National's question about whether the differences they point out could have affected test results came up after the evaluation board was returned to them, so we'd need it back to verify our assumption.
Then there is the matter of running all four of the chip's transceiver channels at once, something we had not originally planned to do. National's technical representative said that he wanted to measure the chip's behavior with full-up operation of all of its channels simultaneously. This is what they considered to be "real world" conditions where the internal noise created by adjacent channels would be there to possibly affect the performance of the channel under test.
Although it was not in
our baseline test plan, we were pleased to honor National's request and
included the extra signal paths required for this (See Fig. 2.) It should be noted that we have run more than
one channel on a chip in some of our other tests, most notably during the
test of the Accelerant SerDes, when a second channel was used as an aggressor
source. The tests of the Broadcom SerDes part also involve running more
than one channel. Until now however, we have not considered it a critical
element of our test plan.
Since we have already tested two other chips in the series without fully loading all available channels, we will most likely not do this unless requested for the remainder of the series. But given the fact that on-chip channel densities are increasing, and with it, an increased chance for coupling-induced noise problems, we are open to considering this as part of our baseline test plan for our second phase of testing.
As we explained in our commentary of the previous test results, our first tests on the Vitesse SerDes were limited by the capabilities of their beta-version evaluation board. Since the chip has receive equalization capability but no on-chip CDR, the test set-up we had to use did not allow us to test the receive side of the chip. In the interest of getting some useful data out to the world, we used the BERT tester as a receiver and made bathtub plots of the performance of the transmit signal only.
The good news is that we now have an improved version of the Vitesse evaluation board that will enable us to perform end-to-end tests that will give us a more complete idea of the chip's capabilities. The bad news is that since it has no on-chip CDR, we will still be unable to produce a pass/fail matrix. But the updated bathtub plots and eye diagrams should provide more realistic data for our readers. We are currently negotiating with Vitesse on whether they want to proceed with the re-test program.
National also pointed out that our tests with the Accelerant SerDes used the chip's internal BERT function rather than our $50-k piece of test equipment. This was done to simplify the test procedure after our researchers satisfied themselves that the on-chip logic would produce results that were every bit as reliable as our equipment could offer. Since we've learned so much since we tested the Accelerant part at the beginning of this project, we're encouraging them to come back for a more thorough run on our test bed. If we can coax them back we will use a regular off-chip BERT to produce a pass/fail matrix comparable to those we'll generate for all subsequent pares we test, and it will give us an opportunity to verify the accuracy of their on-chip BERT capabilities.
Looking Ahead
With a better understanding of what we are doing, and our work on this series of tests well under way, we are beginning to consider a set of follow-on events. We'd like to take what we've learned and apply it to exploring other SerDes-related topics, and perhaps even re-visit some of what we have already covered with more rigorous test criteria.
One of the things we're considering is to try to better define a "legacy" backplane, and how modern silicon copes with the often-challenging environments found there. The "Equalize This!" team will soon begin soliciting inputs from several academics and industry experts about how we might get a better handle on defining the line impairments found in legacy chassis, and how to more closely simulate them in our tests. Other projects under consideration include an evaluation of short-haul copper interconnects and perhaps a survey of the emerging 10-Gbit/s SerDes transceivers.
We hope to open the discussion some time this Spring so we can begin organizing the actual second-phase tests a bit later in the year. We'd welcome comments from readers and other silicon vendors that would help us make our follow-on tests as informative and useful as possible. Please feel free to drop me a line at lgoldberg@green-electronics.com with your critiques, questions & suggestions.
