foolZONE Special Reports for April 1, 2006

April 1, 2006: Ogdensberg, NY...Researchers from a small research lab at the old Zurg building here today announced that in the course of developing the next process node of 30 nm, they have accidentally created a fissure underneath the gate of a CMOS FET that could actually transport electrons without resistance. In a manner much like the way the Jolt-powered 80-hour work weeks have driven Silicon Valley engineers to new heights of performance, this new process that uses overstress techniques to form what they refer to as Fissure FETs (FFets) that are expected to deliver a quantum leap in the speed of solid-state devices.

Art Killingsworth, fourth cousin of the sister-in-law of the neighbor of original transistor inventor John Bardeen, described the accidental discovery, "We were trying to create strain in the gate oxide to get the device speeds beyond those reported by those overfunded post-doc-brats at SigInt's Labs, so the first thing we tried was to dip a 30-nm, non-annealed, CMOS wafer into LN2 -- elegant simplicity. When we ran the curve tracer we saw that the device exhibited absolutely none of the transport, recombination, or resistive effects that we typically see with lattice-based materials."

If the initial results are an indicator, the new FFET structure is nothing short of a breakthrough in three-port electronic devices, heralding a new inflection point in electronics and possibly giving America its technology edge back from up-and-coming technology centers like Bangalore, Shanghai, and Victoria BC.

Officials at Zurg would only describe the F_t of the device as "impressive," but a conversation with one of the co-op interns in the john during a potty break revealed it would probably take UIUC's Milton Feng another 20 years to come even close to this new device's present-day THz speed. (The payback for giving a kid a C+ in device physics can be a boon to any seasoned journalist.)

Killingsworth continued, "After sectioning and polishing a sample transistor site, we discovered a 9 angstrom crack extending for the full depth of the channel, directly below the oxide. You couldn't ask for a more ideal triode-region response and the fractal nature of the fissure increases the surface emitters by seven orders of magnitude over that of a CMP surface profile, meaning we don't get erosion as you would find in cold-cathode emitters."

The region of the crack appears to be well controlled and repeatable, allowing for the possibility of printing billions of such devices onto a silicon substrate. Just as for the first transistors made of Germanium, the next step in this highly-innovative research is to establish process steps to passivate the fissure under high vacuum: trapped molecular, or atomic gases, liquids, or solids, quickly reduce the saturated current capability of the device, as well as causing it to become resistive between the device's source and drain.

Killingsworth added that he expects that perfecting a commercially-viable passivation technique will add six months to a year to the development efforts, but still expects to meet the company's goal of sampling a preliminary product by April 1st, 2008.

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