Microcontroller Design Tradeoffs
by Dennis L. Feucht
Innovatia Laboratories
Power converters and motor drives increasingly have embedded microcontrollers (µCs), if not DSPs. Let's look at some design features and tradeoffs of various µC architectures that can be applied to real-time, embedded power applications.
Register-Based Computing
Atmel has put in an 8-pin DIP or SMD a complete, in-circuit-programmable
controller for a power converter or dc motor drive. Move up to a 20-pin
AT90S2313, which has been sold in the surface-mount package at low volume
for as little as $0.85 by a major component distributor, and you have the
core component of a three-phase motor controller. The AVR parts, like their
PIC competitors by Microchip, have an 8-bit (data) microprocessor core surrounded
by useful I/O, including serial communications, counter/timers, parallel
ports, comparators, ADCs, and PWM generators. The PWM of AVR µCs is
centered; the on-time duration occurs in the middle of the switching cycle.
Interrupts that occur at the end of the switching cycle, and also at the
end of the on-time, trigger the code to switch the bridge to the next state
while PWM drive is off. This reduces stress on bridge power-switches.
Like the PIC, the AVR has a DSP-like architecture. It has a Harvard architecture, which separates program and data memory. The advantage is that there are now two channels from CPU to memory, and instructions and data can simultaneously be transferred. The CPU-memory single-channel limitation, or "Von Neumann bottleneck," is eased somewhat. The only loss of flexibility with separated code and data spaces is that self-modifying code cannot be used. But this is not a significant loss, nor does it apply to most kinds of programming.
These processors are also horizontally microprogrammed, with a long instruction word (16 bits), so that multiple program bits can be applied simultaneously in executing the instruction. This results in single clock cycles for most instructions.
Another DSP-like feature is that the AVR and PIC are register-based. They lack the more powerful addressing modes of conventional (CISC) processors, such as the 6800 or 6502, which provide memory-based indirection and indexing into tables in data memory. In these newer processors, it is even necessary to compute table look-up addresses by keeping the index value in one register and the base address of the table in another. The index register is added to the base address whenever an indexed table address in SRAM is needed. (Or alternatively, the indexed address is kept in a register and a subtraction from the base-address register is used to obtain the index value.) This adds machine cycles to program execution time though, overall, if the registers are used to hold the data under computation fewer data-memory accesses are required. This minimizes the effects of the Von Neumann bottleneck. For programmers used to CISC processors, this DSP-like or RISC (reduced instruction-set computer) architecture at first is frustrating. Register-based computing takes some adjustment in coding technique.
The data-intensive instructions of these register-based processors are dual operand, allowing both data and result registers to be named in one instruction. In accumulator-based, single-operand machines, results are limited to appear in a single accumulator register. More instructions (and machine cycles) are required to move the results to memory or another register from it. By specifying two operands, the result has multiple possible destinations and can be put immediately where it is wanted.
µCs Versus DSPs
The register-based, single-instruction (or RISC) approach to mC architecture
is where DSPs have always been. The only significant difference between
the AVR and, say, Analog Devices, Inc. ADSP2100 series of DSPs is that the
DSPs have a longer instruction word (24 bits for the ADSP21XX), a hardware
multiply (which some mCs now have), a barrel shifter, and address computation
hardware. mCs are evolving into DSPs, and can be considered low-performance,
low-cost DSPs. Meanwhile, DSPs are acquiring more I/O around their cores;
the new ADI ADMCF328 DSP has in-circuit programmability (flash program memory)
and a rather complete set of I/O capabilities for motor control. It is available
in 28-pin DIP or surface-mount packages and sells typically for about $30
(as of July 2002), while the Atmel AT90S2313 is selling around $3. Which
one do you choose?
The classic cost-performance design tradeoff depends mainly on the application volume and required computing bandwidth, not time-to-market, for either processor can be programmed in assembler or high-level languages. Once a computing engine is chosen, over time a large amount of useful code accumulates. This investment of effort will, in the long run, have a great influence upon choice of processor and may even be the determining criterion. For even though code may be written in a high-level language, the software development environment for a different instruction set may need to be different. Development time (and cost) can be highly impacted by having to start at square one with a strange, new compiler. No wonder the 6800 is still thriving over 30 years after its market introduction.
Zero-Operand Machines
On the other end of the operand spectrum from dual-operand RISC machines,
some lesser-known processors are emerging that are instead zero operand.
No data registers are used as such. All data is handled on a hardware stack.
(A stack is an ordering of data items accessed on a last in, first out basis,
like a stack of trays would be.) The top register roughly functions as does
the accumulator in single-operand machines, and all the data items - as
many as needed for the operation - come from the top end of the stack. Data
moves up and down, on and off the stack as operations execute. Memory is
accessed only for more permanent storage of data, such as global variables.
The superior efficiency of stack-based computing has been demonstrated in computing theory, and popular languages are not uncommonly implemented using data stacks. The Motorola 68000 even has instructions facilitating the use of stack frames, to hold local variables for routines. One high-level stack-based language, Forth, has been around about as long as FORTRAN or LISP and continues to be used. It is available for just about any instruction set one can find. Those who use it generally find it to be the superior language for embedded applications, though so many Forth programmers in the '70s were raving about it that it developed somewhat of a "geek" reputation, even among software engineers (whom the rest of the world considers geeks anyway.) With the advent of UNIX, the world went crazy for C, and Forth found a niche as the open-boot firmware standard. It is found as the boot-up system in Sun computers, for instance. Otherwise, Forth persists, mainly among hardware-oriented programmers who still appreciate its productivity benefits. Besides the UNIX influence, Forth probably has not caught on because most programmers prefer names for local variables instead of keeping track of where they are on a stack. Even so, some famous computer applications have been written in Forth. It's a versatile tool for writing languages and user interfaces.
Forth is a logical extension of assembler in that routines are given names and linked into lists which can be searched by the Forth interpreter and are called words. All words have a run-time routine associated with their name, even data. For example, the run-time action of variables is to return the address of the variable on the top of the stack. (Which run-time routine a word invokes places it implicitly into something like an object class.) Most good assembly code is organized hierarchically as a sequence of subroutine calls to lower-level routines. The lowest routines are optimized in machine (assembly) code for performance. Forth has a few machine-dependent words at low level and the rest are compiled using them. Forth allows more words to be added to its "dictionary" by the programmer, and makes no distinction (other than in its standard specification) between Forth words and application words. They are all part of the same openly-extensible computing environment. The words programmers write merely extend the language-defined set, including words for compiling. In contrast, languages such as C have a fixed set of functions. While libraries of routines can be added, the compiler-time capabilities of C are fixed by language definition. Instead, Forth has extensibility comparable to LISP. Newer languages like Java incorporate Forth-like extensibility features.
Zero-operand (or stack-based, or Forth) machines made their first major commercial debut as the Harris RTX2000 series. These processors were relatively expensive and did not succeed in the market, but retreated to a radiation-hardened space use. Since then, Forth's inventor Chuck Moore has developed a fast stack machine, and others have FPGA-based designs. (See www-2.cs.cmu.edu/~koopman/stack_computers/supp.html for a list of commercially-available stack machines.) While stack machines have not caught on for embedded computing, the underlying theory of stack computing, and the elegance known to their enthusiasts, suggests that they eventually will be rediscovered. The advantages are too elementary to be ignored forever.
Power designers seeking an edge in embedded computing technology might
take a look at this class of machines. What limits their use is commercial
availability, lacking a variety of different packages, I/O features, and
software development systems. But that's always true at the leading edge
of technology.
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