The Fundamentals of CMOS Op Amps (Part I)
by "Telegenic"
Introduction
In this series we are going to look at the way CMOS op amps are designed,
how they operate and how their use can be maximized in various applications.
We will try to do this from a practical viewpoint rather than from the academic
approach which usually starts with, "assume a virtual ground at . .
."
The simplest op amp consists of just two stages with a differential input amplifier driving a single-ended output stage. In integration this simple solution can ne performed with 9 transistors (sse Fig. 1.) Four of these (M4 through M7) form the differential input amplifier where th gain is dependent on the transconductance of the input devices (M4 and M6) and the output loading by the drain conductance of the lower pair of devices (M5 and M7.)
The output stage is formed with two devices (M8 and M9) with a gain that
is similar to that of a standard simple inverting amplifier. The upper device
in the output stage (M8) is also part of the network of four devices that
determine the bias network (M2 through M8) with the crterion being to operate
all the devices as at low a current as possible to maximize transconductance.
The small aspect ratio of M2 dervies a gate voltage on M1 that is repeated
on M3 and M8.
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